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Digital filter with efficient quantization circuitry 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/10
출원번호 US-0050391 (1998-03-30)
발명자 / 주소
  • Gandhi Prashant
  • Hochschild James R.
출원인 / 주소
  • Texas Instruments Incorporated
대리인 / 주소
    Williams
인용정보 피인용 횟수 : 44  인용 특허 : 3

초록

An infinite impulse response (IIR) digital filter and method of performing the same is disclosed. The digital filter may be realized by way of a programmable logic device, such as a digital signal processor (75), or alternatively by way of dedicated logic including adders (44, 48, 50, 54, 58, 62, 66

대표청구항

[ We claim:] [1.] A method of determining a feedback value in a digital filter, the feedback value corresponding to a sum of first and second products, the first product corresponding to a first coefficient value times a first output sample value, and the second product corresponding to a second coe

이 특허에 인용된 특허 (3)

  1. Ishibata Naomasa,JPX, Digital filter device having a bit shifter unit.
  2. Leeb Ferenc (Villach ATX) Gazsi Lajos (Dusseldorf DEX), Method for filtering a digital value train with improved noise behavior, and circuit configuration for performing the me.
  3. Satoshi Matsui,JPX, Sum-of-products arithmetic unit.

이 특허를 인용한 특허 (44)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  5. Guttag, Karl M., Allocating memory on a spatial light modulator.
  6. Guttag, Karl M., Allocating registers on a spatial light modulator.
  7. Guttag, Karl M., Allocation registers on a spatial light modulator.
  8. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  9. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  10. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  11. Guttag, Karl M.; Guttag, Alvin, Bit serial control of light modulating elements.
  12. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  13. Huang, Chih-Haur, Delay-locked loop and a stabilizing method thereof.
  14. Yeum,Wang seup, Digital base booster using arithmetic processor.
  15. Ohashi, Masahiro; Aizono, Takeiki; Fujii, Dai; Tanaka, Hiroyuki; Kogure, Makoto, Distributed control system and filtering method used in the distributed control system.
  16. Shen,Jiang, Implementation of digital filter with reduced hardware.
  17. Guttag, Karl M.; Guttag, Alvin, Instructions controlling light modulating elements.
  18. Melanson,John L., Jointly nonlinear delta sigma modulators.
  19. Wang,Minsheng, Limit-cycle oscillation suppression method, system, and computer program product.
  20. Jiang, Zhongnong, Limit-cycle-absent allpass filter lattice structure.
  21. Melanson,John L., Look-ahead delta sigma modulator having an infinite impulse response filter with multiple look-ahead outputs.
  22. Melanson,John L., Look-ahead delta sigma modulator with pruning of output candidate vectors using quantization error minimization pruning techniques.
  23. Melanson,John L., Look-ahead delta sigma modulator with quantization using natural and pattern loop filter responses.
  24. Melanson,John L., Look-ahead delta sigma modulators with quantizer input approximations.
  25. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  26. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  27. Guttag, Karl M., Mapping pixel values.
  28. Pilgram,Berndt, Method and apparatus for suppressing limit cycles in noise shaping filters.
  29. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  30. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  31. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  32. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  33. Knezevic, Miroslav; Nikov, Ventzislav, Optimized hardward architecture and method for ECC point addition using mixed affine-jacobian coordinates over short weierstrass curves.
  34. Knezevic, Miroslav; Nikov, Ventzislav, Optimized hardware architecture and method for ECC point doubling using Jacobian coordinates over short Weierstrass curves.
  35. Knezevic, Miroslav; Nikov, Ventzislav, Optimized hardware architecture and method for ECC point doubling using jacobian coordinates over short weierstrass curves.
  36. Melanson,John L., Overload protection for look-ahead delta sigma modulators.
  37. Melanson,John L., Pattern biasing for look-ahead delta sigma modulators.
  38. Scheuermann,W. James; Frost, III,Otis Lamont, Reconfigurable filter node for an adaptive computing machine.
  39. Guttag, Karl M., Recursive feedback control of light modulating elements.
  40. Melanson,John L., Signal processing with look-ahead modulator noise quantization minimization.
  41. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  42. Chatterjee,Chanchal, Systems and methods for efficient quantization.
  43. Guttag, Karl M., Variable storage of bits on a backplane.
  44. Tatsuoka, Masato, Zero determination signal generating circuit.
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