초록 ▼

A CMOS image sensor is provided in which correlated double sampling is performed entirely in the digital domain. In an exemplary embodiment, the image sensor includes a plurality of imager cells arranged in rows and columns, where the imager cells of a particular column are coupled to a column data

A CMOS image sensor is provided in which correlated double sampling is performed entirely in the digital domain. In an exemplary embodiment, the image sensor includes a plurality of imager cells arranged in rows and columns, where the imager cells of a particular column are coupled to a column data line of that column. Each active imager cell is capable of selectively providing a first output on an associated column data line indicative of a reset level during a first sampling interval. During a second sampling interval, each active imager cell provides a signal output on the associated column data line indicative of an amount of light incident upon that imager cell. At least one analog to digital (A/D) converter is coupled to the column data lines and converts the first and signal outputs on each column data line to first and second digital codes, respectively, to complete a correlated double sampling operation. The invention eliminates the need for analog capacitors to store the reset and signal levels.

대표청구항 ▼

[ What is claimed is:] [1.] An image sensor, comprising:a plurality of imager cells arranged in rows and columns, with the imager cells of any given column being coupled to a column data line of that column, and each imager cell being operable to selectively provide a first output on an associated c

[ What is claimed is:] [1.] An image sensor, comprising:a plurality of imager cells arranged in rows and columns, with the imager cells of any given column being coupled to a column data line of that column, and each imager cell being operable to selectively provide a first output on an associated column data line indicative of a reset level during a first sampling interval and to provide a signal output on the associated column data line during a second sampling interval indicative of an amount of light incident upon that imager cell, each said imager cell comprises a first transistor operative to selectively set a voltage level at a reference node, and a second transistor having a control terminal coupled to said reference node, and an output terminal coupled to the column data line of the column associated with the particular imager cell, said second transistor providing said first output indicative of potential of said reference node during said first sampling interval in which said first transistors is off, and said signal output indicative of potential of the amount of light incident upon that imager cell during said second sampling interval; andat least one analog to digital (A/D) converter coupled to said column data lines for converting at least said first output on each column data line to a first corresponding digital code, to enable a subsequent comparison with a second digital code associated with said signal output to complete a correlated double sampling operation.