초록 ▼

Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, cost, reliability, and a

Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, cost, reliability, and availability goals. The present invention addresses the problem of hardware-software co-synthesis of fault-tolerant real-time heterogeneous distributed embedded systems. Fault detection capability is imparted to the embedded system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. The reliability and availability of the architecture are evaluated during co-synthesis. On embodiment of the present invention, called COFTA, allows the user to specify multiple types of assertions for each task. It uses the assertion or combination of assertions that achieves the required fault coverage without incurring too much overhead. New methods are proposed to: 1) perform fault tolerance based task clustering, which determines the best placement of assertion and duplicate-and-compare tasks, 2) derive the best error recovery topology using a small number of extra processing elements, 3) exploit multi-dimensional assertions, and 4) share assertions to reduce the fault tolerance overhead. The present algorithm can tackle multirate systems commonly found in multimedia applications.

대표청구항 ▼

[ What is claimed is:] [1.] A computer-implemented method for designing the architecture of an embedded system, comprising:(a) a pre-processing phase comprising the steps of:(1) parsing one or more task graphs, one or more system/task constraints, and a resource library for the embedded system; and(

[ What is claimed is:] [1.] A computer-implemented method for designing the architecture of an embedded system, comprising:(a) a pre-processing phase comprising the steps of:(1) parsing one or more task graphs, one or more system/task constraints, and a resource library for the embedded system; and(2) assigning one or more fault detection tasks to one or more original tasks in the task graphs to enable the embedded system to perform fault detection for the one or more original tasks; and(b) a synthesis phase, following the pre-processing phase, comprising the steps of allocating the fault detection tasks and one or more groups of one or more original tasks to one or more processing elements (PEs) in the resource library and allocating one or more edges in the task graphs to one or more communication links in the resource library, based on performance evaluation of one or more possible allocations for each of the groups, edges, and fault detection tasks in light of the system/task constraints, wherein the pre-processing phase comprises the step of performing task clustering on the one or more task graphs to form one or more clusters for the embedded system, wherein task clustering comprises the steps of:(i) assigning a fault tolerance (FT) level to each original task based on execution time, communication time, and any associated fault detection tasks; and(ii) determining an appropriate cluster for each original task based on the FT level in order to reduce FT overhead.