초록 ▼

A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate

A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

대표청구항 ▼

[ What is claimed is:] [1.] A method of forming a sidewall gate structure, comprising the steps of:forming a primary insulation layer adjacent a semiconductor substrate, the semiconductor substrate comprising a first and second doped region separated by a channel region;forming a disposable gate cov

[ What is claimed is:] [1.] A method of forming a sidewall gate structure, comprising the steps of:forming a primary insulation layer adjacent a semiconductor substrate, the semiconductor substrate comprising a first and second doped region separated by a channel region;forming a disposable gate covering a portion of the primary insulation layer proximate the channel region of the semiconductor substrate;forming a sidewall insulation body adjacent to the disposable gate, the sidewall insulation body comprising a silicon oxynitride material;removing the primary insulation layer proximate the first and second doped regions of the semiconductor substrate to expose a portion of the semiconductor substrate;forming an epitaxial layer on the exposed portion of the semiconductor substrate;forming a buffer layer adjacent the epitaxial layer, at least a portion of the disposable gate exposed in the buffer layer;removing the disposable gate to expose a portion of the primary insulation layer proximate the channel region of the semiconductor substrate;removing the exposed portion of the primary insulation layer to expose a channel portion of the semiconductor substrate, the primary insulation layer selectively removable relative to the buffer layer;forming a gate insulator on the exposed channel portion of the semiconductor substrate; andforming a gate adjacent the gate insulator.