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Hardwire logic device emulating an FPGA 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/00
출원번호 US-0937809 (1997-09-29)
발명자 / 주소
  • Law Edwin S.
  • Buch Kiran B.
  • Baxter Glenn A.
  • Pang Raymond C.
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Cartier
인용정보 피인용 횟수 : 68  인용 특허 : 15

초록

A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original

대표청구항

[ What is claimed is:] [1.] A mask programmable integrated circuit (IC) for replacing a field programmable gate array (FPGA), the FGPA having a set of input/output (I/O) blocks, the IC comprising:a gate array core; anda set of mask programmable I/O cells providing an interface between signals in sai

이 특허에 인용된 특허 (15)

  1. Baxter Glenn A. ; Buch Kiran B. ; Pang Raymond C. ; Law Edwin S., Boundary scan chain with dedicated programmable routing.
  2. Assar Mahmud (Morgan Hill CA) Agarwal Prakash C. (San Jose CA) Bril Vlad (Campbell CA), CMOS low power mixed voltage bidirectional I/O buffer.
  3. Chen Ian ; Ko Uming, CPU, memory controller, bus bridge integrated circuits, layout structures, system and methods.
  4. Baxter Glenn A., Configuration emulation of a programmable logic device.
  5. Piccirillo Gary J. (Houston TX) Welker Mark W. (Spring TX) Thayer John S. (Houston TX), Expansion device configuration system having two configuration modes which uses automatic expansion configuration sequen.
  6. Asano Shigehiro (Kanagawa-ken JPX) Isobe Shouzou (Kanagawa-ken JPX) Amemiya Jiro (Kanagawa-ken JPX) Muratani Hirofumi (Kanagawa-ken JPX), High speed logic simulation system using time division emulation suitable for large scale logic circuits.
  7. Andrews William B. ; Britton Barry K. ; Hickey Thomas J. ; Modo Ronald T. ; Nguyen Ho T. ; Schadt Lorraine L. ; Singh Satwant, Hybrid programmable gate arrays.
  8. Buch Kiran B. (Fremont CA) Law Edwin S. (Saratoga CA) Chu Jakong J. (Santa Clara CA), Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays.
  9. Sparks, Steve E.; Edwards, Darvin R.; Heinen, Katherine G., Multi-chip module testing.
  10. Titus Scott Duane ; Martin Kreg A. ; Will Stephen K., Processor device having automatic bus sizing.
  11. Tochio Tatsuya,JPX ; Tada Osamu,JPX ; Oguma Toshio,JPX ; Morimoto Kazunobu,JPX ; Fujii Mototsugu,JPX, Program data creating method and apparatus for use with programmable devices in a logic emulation system.
  12. Gould Scott Whitney ; Keyser ; III Frank Ray ; Larsen Wendell Ray ; Worth Brian Allen, Programmable array interconnect latch.
  13. Becker Steffen (Zorneding DEX) Schmitt-Landsiedel Doris (Ottobrunn DEX) Keitel-Schulz Doris (Munich DEX), Programmable logic array having programmable output driver drive capacity.
  14. Chen Nang-Ping ; Ko Robert J. ; Li Jeong-Tyng ; Huang Thomas B. ; Wang Ming-Yang, Structure and method for providing reconfigurable emulation circuit.
  15. Shimizu Yoji (Yokosuka JPX) Jindo Tomio (Yokohama JPX) Ohshima Shizu (Yokosuka JPX) Hirasago Kiyomi (Yokosuka JPX), System for designing configuration with design elements characterized by fuzzy sets.

이 특허를 인용한 특허 (68)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  11. Heidari-Bateni, Ghobad; Plunkett, Robert Thomas, Adaptive, multimode rake receiver for dynamic search and multipath reception.
  12. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master,Paul L.; Smith,Stephen J.; Watson,John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  19. Hogenauer, Eugene B., Arithmetic node including general digital signal processing functions for an adaptive computing machine.
  20. Howard, Ric; Katragadda, Ramana V., Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture.
  21. de Waal, Abraham B.; Diard, Franck R., Automatic quality testing of multimedia rendering by software drivers.
  22. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  23. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  24. Rubin, Owen Robert; Murray, Eric; Uhrig, Nalini Praba, Consumer product distribution in the embedded system market.
  25. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  26. Huggins Alan H. ; Schmulian David E. ; MacPherson John ; Devanney William L., Designing integrated circuit gate arrays using programmable logic device bitstreams.
  27. Chakraborty, Kanad; Purushotham, Naveen, Embedded memory testing using back-to-back write/read operations.
  28. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  29. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  30. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  31. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  32. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  33. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  34. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  35. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  36. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  37. Edwin S. Law ; Kiran B. Buch ; Glenn A. Baxter ; Raymond C. Pang, Hardwire logic device emulating any of two or more FPGAs.
  38. Master,Paul L.; Hogenauer,Eugene; Scheuermann,Walter James, Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements.
  39. Kapoor, Shakti; Adamane, Prashanth Kumar, I/O stress test.
  40. Furtek, Frederick Curtis; Master, Paul L.; Plunkett, Robert Thomas, Input/output controller node in an adaptable computing environment.
  41. Lien, Jung-Cheun; Feng, Sheng; Sun, Chung-yuan; Huang, Eddy Chieh, Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure.
  42. Heidari-Bateni, Ghobad; Sambhwani, Sharad D., Internal synchronization control for adaptive integrated circuitry.
  43. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  44. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  45. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  46. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  47. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  48. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  49. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  50. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  51. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  52. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  53. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  54. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  55. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  56. Master, Paul L.; Scheuermann, W. James, Method and system for reducing the time-to-market concerns for embedded system design.
  57. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  58. Ebeling, W. H. Carl; Hogenauer, Eugene B., Method, system and software for programming reconfigurable hardware.
  59. Scheuermann,W. James, Processing architecture for a reconfigurable arithmetic node.
  60. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  61. Baxter Glenn A. ; Buch Kiran B. ; Law Edwin S., Programmable IC with gate array core and boundary scan capability.
  62. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas, Secure storage of program code for an embedded system.
  63. Master,Paul L.; Watson,John, Storage and delivery of device features.
  64. Choi,In Young, System and method for creating replacements for obsolete computer chips.
  65. Jacob,Rojit; Chuang,Dan Minglun, System and method using embedded microprocessor as a node in an adaptable computing machine.
  66. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  67. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  68. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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