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Method and apparatus for planarization of metallized semiconductor wafers using a bipolar electrode assembly 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/302
출원번호 US-0096309 (1998-06-11)
발명자 / 주소
  • Adams John A.
  • Krulik Gerald A.
  • Smith Everett D.
출원인 / 주소
  • Integrated Process Equipment Corporation
대리인 / 주소
    Quarles & Brady LLP
인용정보 피인용 횟수 : 65  인용 특허 : 14

초록

Planarization of metal interconnections in semiconductor wafer manufacturing is performed by providing relative motion between a bipolar electrode assembly scanned and a single metallized surface of a semiconductor wafer without necessary physical contact with the wafer or direct electrical connecti

대표청구항

[ We claim:] [1.] A method of bipolar planarizing of a metallized surface of a semiconductor wafer, the method including the steps of:(a) positioning a bipolar electrode assembly proximate to said metallized surface, said bipolar electrode assembly having an anode and cathode separated along an axis

이 특허에 인용된 특허 (14)

  1. Tsai Chia S. (Hsin-chu TWX) Tseng Pin-Nan (Hsin-chu TWX), Chemical/mechanical planarization (CMP) apparatus and polish method.
  2. Shinogi Masataka (Tokyo JPX) Sakuhara Toshihiko (Tokyo JPX) Suda Masayuki (Tokyo JPX) Iwasaki Fumiharu (Tokyo JPX) Ando Akito (Tokyo JPX), Electrochemical fine processing apparatus.
  3. Datta Madhav (Yorktown Heights NY) O\Toole Terrence R. (Webster NY), Electrochemical metal removal technique for planarization of surfaces.
  4. Bernhardt Anthony F. (Berkeley CA) Contolini Robert J. (Pleasanton CA), Electrochemical planarization.
  5. Datta Madhav (Yorktown Heights NY) Shenoy Ravindra V. (Peekskill NY), Electroetching method and apparatus.
  6. Datta Madhav (Yorktown Heights NY) Shenoy Ravindra (Peekskill NY), Electroetching process for seed layer removal in electrochemical fabrication of wafers.
  7. Brophy Denis J. (Staatsburg NY) Datta Madhav (Yorktown Heights NY) Harris Derek B. (Dryden NY) Ryan Frank S. (Boulder CO) Spera Frank A. (Poughkeepsie NY), Electroetching tool using localized application of channelized flow of electrolyte.
  8. Datta Madhav (Yorktown Heights NY) Romankiw Lubomyr T. (Briarcliff Manor NY) Shenoy Ravindra V. (Peekskill NY), Elimination of island formation and contact resistance problems during electroetching of blanket or patterned thin metal.
  9. Mayer Steven T. (Piedmont CA) Contolini Robert J. (Pleasanton CA) Bernhardt Anthony F. (Berkeley CA), Method and apparatus for spatially uniform electropolishing and electrolytic etching.
  10. Schneider Reinhard,DEX, Method and device for continuous uniform electrolytic metallizing or etching.
  11. Kim Young-sun (Seoul KRX) Park Young-wook (Suwon KRX), Method for interconnecting layers in semiconductor device.
  12. Ishida Hirofumi (Hiratsuka JPX), Plating device for wafer.
  13. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
  14. Dinan Thomas E. (Poughkeepsie NY) Berridge Kirk G. (Fishkill NY) Datta Madhav (Yorktown Heights NY) Kanarsky Thomas S. (Hopewell Junction NY) Pike Michael B. (Hopewell Junction NY) Shenoy Ravindra V., Vertical electroetch tool nozzle and method.

이 특허를 인용한 특허 (65)

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  2. Thomas,Terence M.; So,Joseph K., CMP system for metal deposition.
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  4. Andryushchenko,Tatyana N.; Miller,Anne E., Damascene fabrication with electrochemical layer removal.
  5. Lee, Whonchee; Meikle, Scott, Electro-mechanically polished structure.
  6. Kistler, Rodney C., Electrochemical assisted CMP.
  7. Duboust, Alain; Sun, Lizhong; Liu, Feng Q.; Wang, Yuchun; Wang, Yan; Neo, Siew; Chen, Liang-Yuh, Electrolyte composition and treatment for electrolytic chemical mechanical polishing.
  8. Sun, Lizhong; Liu, Feng Q.; Neo, Siew; Tsai, Stan; Chen, Liang-Yuh, Electrolyte with good planarization capability, high removal rate and smooth surface finish for electrochemically controlled copper CMP.
  9. Sun,Lizhong; Liu,Feng Q.; Neo,Siew; Tsai,Stan; Chen,Liang Yuh, Electrolyte with good planarization capability, high removal rate and smooth surface finish for electrochemically controlled copper CMP.
  10. Kobata, Itsuki; Wada, Yutaka; Hiyama, Hirokuni; Saito, Takayuki; Toma, Yasushi; Suzuki, Tsukuru; Kodera, Akira, Electrolytic processing apparatus and electrolytic processing method.
  11. Kobata,Itsuki; Shirakashi,Mitsuhiko; Kumekawa,Masayuki; Saito,Takayuki; Toma,Yasushi; Suzuki,Tsukuru; Yamada,Kaoru; Makita,Yuji; Yasuda,Hozumi, Electrolytic processing device and substrate processing apparatus.
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  14. Lane, Richard H., Electropolished patterned metal layer for semiconductor devices.
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  16. Emesh, Ismail; Chadda, Saket; Korovin, Nikolay; Mueller, Brian, Method and apparatus for electrochemically depositing a material onto a workpiece surface.
  17. Lee,Whonchee; Meikle,Scott G.; Blalock,Guy, Method and apparatus for removing adjacent conductive and nonconductive materials of a microelectronic substrate.
  18. Chopra, Dinesh, Method and apparatus for simultaneously removing multiple conductive materials from microelectronic substrates.
  19. Mayer, Steven T.; Drewery, John S., Method and apparatus for uniform electropolishing of damascene IC structures by selective agitation.
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  23. Lee, Whonchee; Meikle, Scott G.; Blalock, Guy T., Method for forming a microelectronic structure having a conductive material and a fill material with a hardness of 0.04 GPA or higher within an aperture.
  24. Eriksen,Soeren, Method for modifying a metallic surface.
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  26. Lee, Whonchee; Meikle, Scott G.; Blalock, Guy T., Method for removing metal layers formed outside an aperture of a BPSG layer utilizing multiple etching processes including electrochemical-mechanical polishing.
  27. Richard Faubert ; John A. Adams, Method for selective removal of copper.
  28. Lee, Whonchee; Moore, Scott E.; Meikle, Scott G., Method for selectively removing conductive material from a microelectronic substrate.
  29. Chopra,Dinesh, Method for simultaneously removing multiple conductive materials from microelectronic substrates.
  30. Richard H. Lane, Method of patterning noble metals for semiconductor devices by electropolishing.
  31. Reid, Jonathan; Varadarajan, Sesha; Emekli, Ugur, Methods and apparatus for depositing copper on tungsten.
  32. Reid, Jonathan; Varadarajan, Sesha; Emekli, Ugur, Methods and apparatus for depositing copper on tungsten.
  33. Lee, Whonchee; Meikle, Scott G.; Moore, Scott E.; Doan, Trung T., Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate.
  34. Lee,Whonchee; Meikle,Scott G.; Moore,Scott E.; Doan,Trung T., Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate.
  35. Lee,Whonchee; Meikle,Scott G.; Moore,Scott E., Methods and apparatus for electrically and/or chemically-mechanically removing conductive material from a microelectronic substrate.
  36. Lee, Whonchee; Moore, Scott E.; Meikle, Scott G., Methods and apparatus for electrically detecting characteristics of a microelectronic substrate and/or polishing medium.
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