$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method for forming a semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H91L-021/4763
출원번호 US-0104849 (1998-06-25)
발명자 / 주소
  • Watanabe Joy Kimi
  • Herrick Matthew Thomas
  • Sparks Terry Grant
  • Cave Nigel Graeme
출원인 / 주소
  • Motorola Inc.
대리인 / 주소
    Rodriguez
인용정보 피인용 횟수 : 28  인용 특허 : 16

초록

In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher

대표청구항

[ What is claimed is:] [1.] A method for forming a semiconductor device, comprising:forming via-level dielectric film overlying a semiconductor device substrate;forming a trench-level dielectric film directly on and in contact with the via-level dielectric film;etching a via opening in the trench-le

이 특허에 인용된 특허 (16)

  1. Watts David ; Bajaj Rajeev ; Das Sanjit ; Farkas Janos ; Dang Chelsea ; Freeman Melissa ; Saravia Jaime A. ; Gomez Jason ; Cook Lance B., Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture.
  2. Farkas Janos ; Bajaj Rajeev ; Freeman Melissa ; Watts David K. ; Das Sanjit, Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers.
  3. McTeer Allen, Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with c.
  4. Dai Chang-Ming,TWX ; Huang Jammy Chin-Ming,TWX, Dual damascene process using single photoresist process.
  5. Jain Ajay ; Lucas Kevin, Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC).
  6. Misra Veena ; Venkatesan Suresh ; Hobbs Christopher C. ; Smith Brad ; Cope Jeffrey S. ; Wilson Earnest B., Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligne.
  7. Lin Benjamin Szu-Min,TWX ; Jenq Jason,TWX, Method for forming dual damascene structure.
  8. Wetzel Jeffrey T. ; Stankus John J., Method of forming a semiconductor device having dual inlaid structure.
  9. Matsuura Masazumi,JPX, Method of making a semiconductor device.
  10. Dai Chang-Ming,TWX, Method of self-aligned dual damascene patterning using developer soluble arc interstitial layer.
  11. Dai Chang-Ming,TWX, Opposed two-layered photoresist process for dual damascene patterning.
  12. Ong T. P. ; Fiordalice Robert W. ; Venkatraman Ramnath ; Weitzman Elizabeth J., Process for fabricating a metallized interconnect.
  13. Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA), Simplified dual damascene process for multi-level metallization and interconnection structure.
  14. Nguyen Tue ; Charneski Lawrence J. ; Evans David R. ; Hsu Sheng Teng, System and method of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides.
  15. Jolly Gurvinder (Orleans CAX) Yung Bud K. (Ottawa CAX), Tapering sidewalls of via holes.
  16. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (28)

  1. Woo, Christy Mei-Chu; Wang, Pin-Chin Connie; Bernard, Joffre F., Barrier-to-seed layer alloying in integrated circuit interconnects.
  2. Hong,Hyesook; Xing,Guoqiang; Jiang,Ping, Dual cap layer in damascene interconnection processes.
  3. Ott,Andrew; Wong,Lawrence; Morrow,Patrick; Leu,Jihperng; Kloster,Grant M., Dual-damascene interconnects without an etch stop layer by alternating ILDs.
  4. Hsu, Yu-Hao; Chen, Ming-Tsung, Fabricating method of an interconnect structure.
  5. Nakata, Yoshihiro; Fukuyama, Shun-ichi; Suzuki, Katsumi; Yano, Ei; Owada, Tamotsu; Sugiura, Iwao, Low dielectric constant film material, film and semiconductor device using such material.
  6. Nakata,Yoshihiro; Fukuyama,Shun ichi; Suzuki,Katsumi; Yano,Ei; Owada,Tamotsu; Sugiura,Iwao, Low dielectric constant film material, film and semiconductor device using such material.
  7. Koichi Ikeda JP; Masanaga Fukasawa JP; Hideyuki Kito JP; Toshiaki Hasegawa JP, Low dielectric constant insulating films with laminated carbon-containing silicon oxide and organic layers.
  8. Minh Van Ngo ; Christy Mei-Chu Woo, Low dielectric constant stop layer for integrated circuit interconnects.
  9. Lehr, Matthias; Schaller, Matthias; Peters, Carsten, Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same.
  10. Nobuo Aoi JP, Method for forming porous forming film wiring structure.
  11. Ishizuka, Shuichi, Method for manufacturing a semiconductor device having a fluorine containing carbon inter-layer dielectric film.
  12. Ji, Bing; Edelberg, Erik A.; Yanagawa, Takumi; Huang, Zhisong; Li, Lumin, Method for plasma etching performance enhancement.
  13. Lee Fu-Sheng,TWX ; Chen Chien-Chen,TWX ; Lin Chen-Ting,TWX ; Lu Cheh-Chieh,TWX, Method for processing and integrating copper interconnects.
  14. Aoi, Nobuo, Method of forming a porous film on a substrate.
  15. Fei Wang ; Lynne A. Okada ; Ramkumar Subramanian ; Calvin T. Gabriel, Method of making a slot via filled dual damascene structure with middle stop layer.
  16. Fei Wang ; Lynne A. Okada ; Ramkumar Subramanian ; Calvin T. Gabriel, Method of making a slot via filled dual damascene structure with middle stop layer.
  17. Miyata Koji,JPX ; Hasegawa Toshiaki,JPX ; Taguchi Mitsuru,JPX, Method of manufacturing a semiconductor device.
  18. Fujisawa, Masahiko; Ohsaki, Akihiko; Morimoto, Noboru, Method of manufacturing structure for connecting interconnect lines including metal layer with thickness larger than thickness of metallic compound layer.
  19. Takashi Noma JP; Masaji Hara JP; Kimihide Saito JP; Ryo Kawai JP; Yoichi Kanuma JP; Kazuo Okada JP, Non-volatile semiconductor memory device with barrier and insulating films.
  20. Mukherjee, Shyama; Levert, Joseph; DeBear, Donald, Planarizers for spin etch planarization of electronic components.
  21. Aoi, Nobuo, Porous, film, wiring structure, and method of forming the same.
  22. Aoki, Hidemitsu; Tomimori, Hiroaki, Removing solution, cleaning method for semiconductor substrate, and process for production of semiconductor device.
  23. Aoki,Hidemitsu; Tomimori,Hiroaki, Removing solution, cleaning method for semiconductor substrate, and process for production of semiconductor device.
  24. Fujisawa, Masahiko; Ohsaki, Akihiko; Morimoto, Noboru, Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer.
  25. You, Lu; Woo, Christy; Wang, Pin Chin Connie, Use of ta/tan for preventing copper contamination of low-k dielectric layers.
  26. Fei Wang ; Lynne A. Okada ; Ramkumar Subramanian ; Calvin T. Gabriel, Via filled dual damascene structure with middle stop layer and method for making the same.
  27. Kraft,Robert, Via formation for damascene metal conductors in an integrated circuit.
  28. Brase, Gabriela; Schroeder, Uwe Paul; Holloway, Karen Lynne, `Via first` dual damascene process for copper metallization.

관련 콘텐츠

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로