초록 ▼

The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control

The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

대표청구항 ▼

[ What is claimed is:] [1.] A programmable data flow processor operable for performing data transfers between a plurality of devices, the data flow processor comprising:a plurality of ports each for coupling to a device;programmable configuration registers which are operable to receive data forprogr

[ What is claimed is:] [1.] A programmable data flow processor operable for performing data transfers between a plurality of devices, the data flow processor comprising:a plurality of ports each for coupling to a device;programmable configuration registers which are operable to receive data forprogramming the data flow processor for data transfers between selected ones of said plurality of ports;a stream processor coupled to each of said plurality of ports and coupled to said programmable configuration registers, wherein the stream processor is operable to access data comprised in said programmable configuration registers and in response configure a plurality of data streams between said plurality of ports, wherein each of said plurality of data streams is transferred between at least one source port and at least one destination port, and wherein said stream processor is operable to transfer said plurality of data streams between said plurality of ports;wherein the data flow processor includes at least one buffer for temporarily storing data transferred between two devices; andwherein the stream processor determines an ordering of transfers between said plurality of ports based on buffer availability.