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An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indicator or indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be

An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indicator or indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be transferred, or both. The indication bits are provided in a software prefetch instruction such that at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction. Thus, it is not necessary to change the timing for executing a software prefetch instruction depending on which one of the caches of the hierarchical levels is hit, and a compiler can generate an instruction sequence more easily.

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[ What is claimed is:] [1.] An information processing system, comprising:a main memory;a cache; anda processing unit which executes a predetermined software prefetch instruction included as one of a plurality of instructions of a computer program,wherein said predetermined software prefetch instruct

[ What is claimed is:] [1.] An information processing system, comprising:a main memory;a cache; anda processing unit which executes a predetermined software prefetch instruction included as one of a plurality of instructions of a computer program,wherein said predetermined software prefetch instruction, when executed, causes said processing unit to perform a prefetch operation by transferring operand data to be used in a subsequent operation from said main memory to said cache prior to executing said subsequent operation,wherein said predetermined software prefetch instruction includes at least one indication bit for indicating a content of said prefetch operation, said at least one indication bit being included in an operation code or an operand address of said predetermined software prefetch instruction,wherein said cache comprises two hierarchical levels of caches, andwherein said at least one indication bit specifies a hierarchical level of a cache to which said operand data is to be prefetched.