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Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/8238
출원번호 US-0358985 (1999-07-22)
발명자 / 주소
  • Zhu Min,SGX
  • Shao Kai,SGX
  • Chu Shao-Fu Sanford,SGX
출원인 / 주소
  • Chartered Semiconductor Manufacturing Ltd., SGX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 47  인용 특허 : 4

초록

A method for reducing the capacitive coupling of an inductor on an integrated circuit chip is described. The method forms the inductor over an accumulation of dielectric layers used elsewhere in the integrated circuit. In addition two back-to-back reversed p/n junctions are formed within the silicon

대표청구항

[ What is claimed is:] [1.] A method for forming an inductor on a silicon wafer substrate comprising the steps of:(a) providing a silicon wafer of a first conductivity type;(b) patterning a first photoresist layer to define a first opening in a region of said wafer whereover an inductor is to be for

이 특허에 인용된 특허 (4)

  1. Xie Ya-Hong, Integrated circuit device with inductor incorporated therein.
  2. Yu Hyun-Kyu,KRX ; Park Min,KRX, Method for forming an inductor devices using substrate biasing technique.
  3. Abidi Asad A. (Los Angeles CA) Chang James Y.-C. (Los Angeles CA), Monolithic passive component.
  4. Desaigoudar Chan M. (Los Gatos CA) Gupta Suren (San Jose CA), Thin film inductors, inductor network and integration with other passive and active devices.

이 특허를 인용한 특허 (47)

  1. Chen, Chun-Ying, Biasing device for low parasitic capacitance in integrated circuit applications.
  2. Furuya, Shigeki; Watanabe, Hisaki; Mototani, Atsushi, CMOS basic cell and method for fabricating semiconductor integrated circuit using the same.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
  4. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
  5. Huang, Chi-Feng; Chen, Chia-Chung; Liang, Victor Chiang; Lee, Hsiao-Chun, Dual DNW isolation structure for reducing RF noise on high voltage semiconductor devices.
  6. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  7. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  8. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  9. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
  10. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
  11. Horikawa, Yasuyoshi; Nakanishi, Tsukasa; Denda, Tatsuaki, Inductor device and method of manufacturing the same.
  12. Ting-Wah Wong, Integrated inductive circuits.
  13. Wong, Ting-Wah; Woo, Chong L., Integrated radio frequency circuits.
  14. Wong,Ting Wah; Woo,Chong L., Integrated radio frequency circuits.
  15. Coolbaugh,Douglas D.; Erturk,Mete; He,Zhong Xiang; Stamper,Anthony K., Method for high performance inductor fabrication using a triple damascene process with copper BEOL.
  16. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  17. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  18. Hsu, Heng-Ming; Chung, Jau-Yuann; Ho, Yen-Shih; Chen, Chun-Hon; Peng, Kuo-Reay; Yeh, Ta-Hsun; Thei, Kong-Beng; Ma, Ssu-Pin, Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process.
  19. Contopanagos, Harry; Komninakis, Christos; Kyriazidou, Sissy, Method of manufacturing an on-chip inductor having improved quality factor.
  20. Yelehanka,Pradeep; Chu,Sanford; Ng,Chit Hwei; Zhen,Jia; Verma,Purakh, Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits.
  21. Nakayama,Fumitaka; Morikawa,Masatoshi; Hoshino,Yutaka; Uchiyama,Tetsuo, Multilayered semiconductor structure containing a MISFET, a resistor, a capacitor, and an inductor.
  22. Aton, Thomas J., On-chip capacitor.
  23. Aton, Thomas J., On-chip capacitor.
  24. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  25. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  26. Wong, Ting-Wah; Woo, Chong L.; Szeto, Clement, Reducing magnetic coupling using triple well.
  27. Nakayama, Fumitaka; Morikawa, Masatoshi; Hoshino, Yutaka; Uchiyama, Tetsuo, Semiconductor device and manufacturing the same.
  28. Nakayama, Fumitaka; Morikawa, Masatoshi; Hoshino, Yutaka; Uchiyama, Tetsuo, Semiconductor device and manufacturing the same.
  29. Nakayama,Fumitaka; Morikawa,Masatoshi; Hoshino,Yutaka; Uchiyama,Tetsuo, Semiconductor device and manufacturing the same.
  30. Itoi,Kazuhisa; Sato,Masakazu; Ito,Tatsuya, Semiconductor device having gate electrode connection to wiring layer.
  31. Alshareef,Husam N.; Visokay,Mark R.; Rotondaro,Antonio Luis Pacheco; Colombo,Luigi, Semiconductor device having multiple work functions and method of manufacture therefor.
  32. Nakayama,Fumitaka; Morikawa,Masatoshi; Hoshino,Yutaka; Uchiyama,Tetsuo, Semiconductor device including multiple wiring layers and circuits operating in different frequency bands.
  33. Jou Chewnpu,TWX, Semiconductor inductor.
  34. Lee, Chih-Cheng; Su, Yuan-Chang; Shih, Yu-Lin; Yen, You-Lung, Semiconductor package including dielectric layers defining via holes extending to component pads.
  35. Wedley, Timothy Craig, Surge protection apparatus and methods.
  36. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  37. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  38. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  39. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  40. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  43. Zhang, Ying, Tunneling field effect transistor (TFET) formed by asymmetric ion implantation and method of making same.
  44. Zhang, Ying, Tunneling field effect transistor (TFET) formed by asymmetric ion implantation and method of making same.
  45. Zhang, Ying, Tunneling field effect transistor (TFET) with ultra shallow pockets formed by asymmetric ion implantation and method of making same.
  46. Zhang, Ying, Tunneling field effect transistor (TFET) with ultra shallow pockets formed by asymmetric ion implantation and method of making same.
  47. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
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