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A method for manufacturing a memory array having a plurality of memory cells thereon and diffusion areas therebetween includes the steps of laying down a layer of silicon nitride, defining the diffusion areas and creating diffusion oxides over the diffusion areas. Both steps of laying down and defin

A method for manufacturing a memory array having a plurality of memory cells thereon and diffusion areas therebetween includes the steps of laying down a layer of silicon nitride, defining the diffusion areas and creating diffusion oxides over the diffusion areas. Both steps of laying down and defining occur without etching any part of the layer of silicon nitride. The step of creating diffusion oxides includes the steps of creating porous silicon nitride from portions of the silicon nitride layer wherever diffusion oxides are desired (typically by laying down photoresist in a desired pattern and bombarding the silicon nitride layer with ions) and oxidizing both the porous silicon nitride and the silicon substrate through the porous silicon nitride thereby to create silicon oxy-nitride and silicon dioxide, respectively. The present invention also includes a semiconductor chip having diffusion or bit line oxides formed of at least silicon oxy-nitride.

대표청구항 ▼

[ We claim:] [1.] A method for manufacturing a memory array having a plurality of memory cells thereon and diffusion areas therebetween, said memory cells having silicon nitride therein, the method comprising the steps of:laying down a layer of silicon nitride;defining said diffusion areas without e

[ We claim:] [1.] A method for manufacturing a memory array having a plurality of memory cells thereon and diffusion areas therebetween, said memory cells having silicon nitride therein, the method comprising the steps of:laying down a layer of silicon nitride;defining said diffusion areas without etching any part of said layer of silicon nitride; andcreating diffusion oxides over said diffusion areas without etching any part of said layer of silicon nitride.