초록 ▼

Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metall

Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metallization layer over the etch stop layer. Forming a hard mask layer over the conductive via metallization layer. The process further includes producing a conductive via and an interconnect line, where the conductive via is formed from a portion of the conductive via metallization layer, and the interconnect line is formed from a portion of the first interconnect metallization layer. The conductive via is substantially aligned with the underlying interconnect line.

대표청구항 ▼

[ What is claimed is:] [11.] A semiconductor structure, comprising:a substrate having at least one active device;a first dielectric layer lying over the substrate;a first metal interconnect line being patterned over the surface of the first dielectric layer, wherein the first metal interconnect line

[ What is claimed is:] [11.] A semiconductor structure, comprising:a substrate having at least one active device;a first dielectric layer lying over the substrate;a first metal interconnect line being patterned over the surface of the first dielectric layer, wherein the first metal interconnect line is a tri-layer including a first barrier layer, an aluminum/copper layer and an anti-reflective layer;an etch stop layer lying over the first metal interconnect line that is patterned over the surface of the first dielectric layer; anda discrete conductive via structure lying over the etch stop layer that is over the first metal interconnect line, the discrete conductive via structure being substantially perpendicularly aligned with the first metal interconnect line, the first metal interconnect line and the discrete conductive via are perpendicularly aligned due to an etching through a hard mask that is configured to define the discrete conductive via structure and the first metal interconnect line.