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Redefinable signal processing subsystem 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0060745 (1998-04-15)
발명자 / 주소
  • Hudson Michael
  • Moore Daniel L.
출원인 / 주소
  • Diamond Multimedia Systems, Inc.
대리인 / 주소
    Rosenberg
인용정보 피인용 횟수 : 71  인용 특허 : 24

초록

A system in accordance with the invention allows a signal processing system to be configured to perform almost any signal processing function. Such a system includes a redefinable signal processing subsystem and a function-specific module. The system can be defined to perform a particular function b

대표청구항

[ What is claimed is:] [1.] A functionally redefineable signal processing subsystem, comprising:a) a module interface supporting a function-specific module;b) a DSP in communication with said module interface for communicating data between said subsystem and said function-specific module;c) a host i

이 특허에 인용된 특허 (24)

  1. Ueltzen Ken (Rocklin CA) Mahan Andrew M. (Sacramento CA) Horn John A. (Davis CA), Apparatus and method for configuring a computer system and a modem for use in a particular country.
  2. Ogawara Hideki (Kawasaki JPX) Furukawa Hiroshi (Kawasaki JPX), Apparatus having a plurality of programmable logic processing units for self-repair.
  3. Matz Bret A. (Harrisburg PA) Babu K. C. (Kerala INX) Kumar ; K. R. Hemant (Bangalore INX), Cable type identifying and impedance matching arrangement.
  4. Dickie James P. (Corvallis OR) Rabinowitz David M. (Corvallis OR), Dynamically configured computing device.
  5. Martel Sylvain ; Lafontaine Serge R. ; Hunter Ian W., Dynamically reconfigurable hardware system for real-time control of processes.
  6. Halahmi Dror,ILX, Efficient ROM and PLA recoding to save chip area.
  7. Lenihan John P. (Wheaton IL) Dezonno Anthony J. (Downers Grove IL), Functionally programmable PCM data analyzer and transmitter for use in telecommunication equipment.
  8. Chen Chengwu (Sacramento CA) Pierce Michael E. (Sacramento CA) Foote ; III James L. (Sacramento CA), High speed access to PC card memory using interrupts.
  9. Gilson Kent L. (Salt Lake City UT), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
  10. Thomas Nicholas A. (Salt Lake City UT) Evans John (Riverton UT) Bentley Richard (South Jordan UT) Gray Mark L. (West Valley City UT), Method and apparatus for adapting a communication interface device to multiple networks.
  11. Fuller Gregory W. (Boca Roton FL) Fennell Robert D. (Coral Springs FL) Macko William J. (West Palm Beach FL), Method and apparatus for loading a software program from a radio modem into an external computer.
  12. Serrano Arthur L. (23660 Arminta St. Canoga Park CA 91304) Holman Andrew W. (24230 Archwood Canoga Park CA 91304), Microprocessor controlled interface for cellular system.
  13. Dykes Don A. (Houston TX) Castell Robin T. (Spring TX) Clark Andrew C. (Houston TX) Nagel Paul E. (The Woodlands TX) Tran Huyen B. (Houston TX) Jones Randall L. (Plano TX) Baldridge Ronald L. (Carrol, Modem for tight coupling between a computer and a cellular telephone.
  14. Needham David B. (Kissimmee FL), Multimedia interface device and method.
  15. Kou James ; Koo Juliana, PCMCIA card dynamically configured in first mode to program FPGA controlling application specific circuit and in secon.
  16. Pleva Robert M. (Livermore CA) Catlin Robert W. (Santa Clara CA), Personal computer bus interface chip with multi-function address relocation pins.
  17. Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX), Programmable digital signal processor for performing a plurality of signal processings.
  18. Taylor Brad, Programmable logic device for real time video processing.
  19. Sainton Joseph B. (Allen TX), Programmable universal interface system.
  20. Hochfield Barry (Noisy le Roi FRX) Bocquet Nicolas (Paris FRX), Reconfigurable modem for a computer or the like.
  21. Ponte Christian,FRX, Smart debug interface circuit for efficiently for debugging a software application for a programmable digital processor.
  22. O\Sullivan Harry M. (Red Oak TX), System and method for interfacing computers to diverse telephone networks.
  23. Arends Gregory J. (Rochester MN), System for identifying common formats and protocols and allocating respective buffers spaces for simultaneous communicat.
  24. Braitberg Michael F. (Boulder CO) Kennedy Patrick J. (Boulder CO) Sakurai Hiroshi (Tokyo JPX), Universal connection for cellular telephone interface.

이 특허를 인용한 특허 (71)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  7. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  8. El-Kik Tony S., Apparatus for developing internal ROM code using a ROM bus external interface.
  9. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  10. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  15. Wu, Chun-Cheng; Lien, Chia-Chun, Chipset with LPC interface and data accessing time adapting function.
  16. Sebastian Gracias IN; Jim Beaney, Code swapping techniques for a modem implemented on a digital signal processor.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  19. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  20. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  21. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  22. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  23. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  24. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  25. Nicol, Christopher John, Instruction paging in reconfigurable fabric.
  26. Smith, Wesley; Nordling, Karl; Hindie, Amir; Leinfelder, Karl; Gracias, Sebastian; Beaney, Jim, Integrated audio and modem device.
  27. Smith, Wesley; Nordling, Karl; Hindie, Amir; Leinfelder, Karl; Gracias, Sebastian; Beaney, Jim, Integrated audio and modem device.
  28. Poznanovic,Daniel, Interface for integrating reconfigurable processors into a general purpose computing system.
  29. Nicol, Christopher John, Logical elements with switchable connections.
  30. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  31. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  32. Bolourchi, Nader; Terry, Stephen E.; Dick, Stephen G., Method and apparatus for processing a downlink shared channel.
  33. Bolourchi, Nader; Terry, Stephen E.; Dick, Stephen G., Method and apparatus for processing a downlink shared channel.
  34. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  35. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  36. Bolourchi, Nader; Terry, Stephen E.; Dick, Stephen G., Method and system for implicit user equipment identification.
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  42. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  46. Liu, Ming-Kang, Mixed hardware/software architecture and method for processing communications.
  47. Liu, Ming-Kang, Mixed hardware/software architecture and method for processing xDSL communications.
  48. Hindie, Amir; Leinfelder, Karl, Modem instructions sequentially alternating executions between sending a predetermined number of symbols by a transmit sequencer and receiving by a receive sequencer.
  49. Hindie, Amir; Leinfelder, Karl, Modem using a digital signal processor and separate transmit and receive sequencers.
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  51. Sinibaldi, John C.; Parikh, Himanshu; Kulkarni, Veerbhadra S.; Frye, David A.; Turbeville, Gary L, Multi-purpose WAN driver for DSP resource adapter.
  52. Betz,Steve Craig; Wittman,Brian Albert, Multiple function modem including external memory adapter.
  53. Liu,Ming Kang, Physical medium dependent sub-system with shared resources for multiport xDSL system.
  54. Nicol, Christopher John, Power control within a dataflow processor.
  55. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  56. Liu, Ming-Kang, Programmable task scheduler.
  57. Liu,Ming Kang, Scaleable architecture for multiple-port, system-on-chip ADSL communications systems.
  58. Nicol, Christopher John; Chaudhuri, Samit; Danilak, Radoslav, Software based application specific integrated circuit.
  59. Zeev Collin IL; Tal Tamir IL, Software modem having a multi-task plug-in architecture.
  60. Master,Paul L.; Watson,John, Storage and delivery of device features.
  61. Liu,Ming Kang, System and method for a family of digital subscriber line (XDSL) signal processing circuit operating with an internal clock rate that is higher than all communications ports operating with a pluralit.
  62. Jacob,Rojit, System and method using embedded microprocessor as a node in an adaptable computing machine.
  63. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  64. David Pearce ; Wesley Smith ; Karl Nordling ; Amir Hindie ; Karl Leinfelder ; Sebastian Gracias IN; Jim Beaney, System for dedicating a host processor to running one of a plurality of modem programs and dedicating a DSP to running another one of the modem programs.
  65. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  66. Beaney, Jim, Tone detector for use in a modem.
  67. Liu,Ming Kang, Transport convergence sub-system with shared resources for multiport xDSL system.
  68. Falardeau, Brian D., Unified memory architecture for use by a main processor and an external processor and method of operation.
  69. Liu,Ming Kang, xDSL communications systems using shared/multi-function task blocks.
  70. Liu,Ming Kang, xDSL function ASIC processor and method of operation.
  71. Liu, Ming-Kang, xDSL symbol processor and method of operating same.
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