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Determining thresholds and wrap-around conditions in a first-in-first-out memory supporting a variety of read and write transaction sizes

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/02
출원번호 US-0015415 (1998-01-29)
발명자 / 주소
  • L'Ecuyer Brian Peter
출원인 / 주소
  • Hewlett-Packard Company
인용정보 피인용 횟수 : 30  인용 특허 : 3

초록

Data is read from a first-in-first-out (FIFO) queue. A first condition flag is generated which indicates whether a read transaction of a first transaction size may be performed. When a write address for the FIFO queue is greater than a read address for the FIFO queue, the first condition flag is set

대표청구항

[ I claim:] [1.] A method for transferring data in a first-in-first-out (FIFO) queue using a variety of transaction sizes, the method comprising the following steps:(a) generating a plurality of condition flags, each condition flag indicating whether a read transaction of a particular transaction si

이 특허에 인용된 특허 (3)

  1. Ward Morris D. (Garland TX) Williams Kenneth L. (Dallas TX), Cascadable first-in, first-out memory.
  2. Kreifels Gerard A. (7304 Amsterdam Ave. Citrus Heights CA 95621), FIFO with almost full/almost empty flag.
  3. Barringer David (Milpitas CA), Polled FIFO flags.

이 특허를 인용한 특허 (30)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  7. Fedorkow,Guy C.; Muntz,Gary S., Apparatus and technique for conveying per-channel flow control information to a forwarding engine of an intermediate network node.
  8. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  9. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  10. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  11. Bello, Keith Anthony; Friauf, Cheryl Marie; Kishi, Gregory Tad; Norman, Mark Allan, Apparatus, system, and method for optimizing recall of logical volumes in a virtual tape server.
  12. Howard, Ric; Katragadda, Ramana V., Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture.
  13. Howard,Ric; Katragadda,Ramana V., Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture.
  14. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  15. Jiang,Hongtao Jiang, Data interface including gray coding.
  16. Chris Randall Stone ; Ritesh Radheshyam Agrawal, Data processing system having a fifo buffer with variable threshold value based on input and output data rates and data block size.
  17. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  18. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  19. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  20. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  21. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  22. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  23. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  24. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  25. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  26. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  27. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  28. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  29. Jiang, Hongtao, Method of scalable gray coding.
  30. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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