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Method of making spiral-type RF inductors having a high quality factor (Q)

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/20
출원번호 US-0385525 (1999-08-30)
발명자 / 주소
  • Chu Shau-Fu Sanford,SGX
  • Chew Kok Wai Johnny,SGX
  • Chua Chee Tee,SGX
  • Cha Cher Liang,SGX
출원인 / 주소
  • National University of Singapore, SGX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 27  인용 특허 : 8

초록

A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacture of integrated circuits is described. A metal line is provided overlying a dielectric layer on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the metal line and the diel

대표청구항

[ What is claimed is:] [1.] A method of fabricating an inductor in the fabrication of an integrated circuit comprising:providing a metal line overlying a dielectric layer on a semiconductor substrate;depositing an intermetal dielectric layer overlying said metal line and said dielectric layer;patter

이 특허에 인용된 특허 (8)

  1. Shiga Nobuo (Kanagawa JPX), Inductance element.
  2. Merrill Richard Billings ; Archer Donald M., Integrated inductor.
  3. Michael Mark W. ; Dawson Robert ; Hause Fred N. ; Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Brennan William S., Interlevel dielectric with air gaps to reduce permitivity.
  4. Tsui Bing-Yue,TWX, Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrat.
  5. Chang Mark S. (Los Altos CA) Cheung Robin W. (Cupertino CA), Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed perfo.
  6. Stoltz Richard A. (Plano TX) Tigelaar Howard (Allen TX) Cho Chih-Chen (Richardson TX), Method of forming air gap dielectric spaces between semiconductor leads.
  7. Abidi Asad A. (Los Angeles CA) Chang James Y.-C. (Los Angeles CA), Monolithic passive component.
  8. Desaigoudar Chan M. (Los Gatos CA) Gupta Suren (San Jose CA), Thin film inductors, inductor network and integration with other passive and active devices.

이 특허를 인용한 특허 (27)

  1. Chen,Chung Hui, Deep submicron CMOS compatible suspending inductor.
  2. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  3. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  4. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  5. Yen, Hsiao-Tsung; Lin, Yu-Ling, Inductors with through VIAS.
  6. Norstrom, Hans; Bjormander, Carl; Johansson, Ted, Integrated circuit inductor structure and non-destructive etch depth measurement.
  7. Tang, Jinbang; Frear, Darrel R.; Wenzel, Robert J., Integrated circuit module with integrated passive device.
  8. Chen, Zhen; Lin, Yung Feng; Huang, Lin, Integrated inductor.
  9. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  10. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  11. Harris,Edward B.; Downey,Stephen W., Method of forming a spiral inductor in a semiconductor substrate.
  12. Chan, Lap; Chew, Kok Wai Johnny; Cha, Cher Liang; Chua, Chee Tee, Method to fabricate horizontal air columns underneath metal inductor.
  13. Chan,Lap; Chew,Kok Wai Johnny; Cha,Cher Liang; Chua,Chee Tee, Method to fabricate horizontal air columns underneath metal inductor.
  14. Chan Lap ; Chew Johnny Kok Wai,SGX ; Cha Cher Liang,SGX ; Chua Chee Tee,SGX, Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology.
  15. Chaudhry, Samir; Layman, Paul Arthur; Thomson, J. Ross; Laradji, Mohamed; Griglione, Michelle D., Multi-layer inductor formed in a semiconductor substrate.
  16. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  17. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  18. Combi, Chantal; Fiorito, Matteo; Mottura, Marta; Visalli, Giuseppe; Vigna, Benedetto, Process for manufacturing a semiconductor wafer integrating electronic devices including a structure for electromagnetic decoupling.
  19. Harris,Edward B.; Downey,Stephen W., Spiral inductor formed in a semiconductor substrate.
  20. Chaudhry, Samir; Layman, Paul Arthur; Thomson, J. Ross; Laradji, Mohamed; Griglione, Michelle D., Thin film multi-layer high Q transformer formed in a semiconductor substrate.
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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