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Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0294048 (1999-04-19)
발명자 / 주소
  • Chan Lap
  • Zheng Jia Zhen,SGX
출원인 / 주소
  • Chartered Semiconductor Manufacturing Ltd., SGX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 63  인용 특허 : 11

초록

A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is preven

대표청구항

[ What is claimed is:] [5.] A method for manufacturing a copper connector in an integrated circuit comprising:(a) providing a silicon substrate,(b) depositing a first insulating layer on said silicon substrate to a predetermined thickness, said first insulating layer having a top surface and a botto

이 특허에 인용된 특허 (11)

  1. Lee Tze-Liang,TWX, Fabrication process for copper structures.
  2. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  3. Nogami Takeshi, Method and system for electrical coupling to copper interconnects.
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  5. Givens John H. ; Lane Richard H., Method for fabricating conductive components in microelectronic devices and substrate structures thereof.
  6. Nakasaki Yasushi (Yokohama JPX), Method of manufacturing a semiconductor device with a copper wiring layer.
  7. Hoshino Kazuhiro (Tokyo JPX), Method of producing semiconductor device.
  8. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  9. Yakura James P., Non-linear circuit elements on integrated circuits.
  10. Tokunaga Takafumi (Tokorozawa JPX) Tsuneoka Masatoshi (Ohme JPX) Mizukami Koichiro (Akishima JPX), Process for producing semiconductor integrated circuit device having copper interconnections and/or wirings, and device.
  11. Li Jian (Ithaca NY) Mayer James W. (Phoenix AZ) Colgan Evan G. (Suffern NY) Gambino Jeffrey P. (Gaylordsville CT), Self-aligned process for capping copper lines.

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