초록 ▼

A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by performing the electrochemical

A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by performing the electrochemical deposition of copper in two deposition stages with an dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brightener and leveler. The first deposition is done at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio contact/via openings are covered with a substantial thickness of a uniform, high quality copper coating. During the deposition, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. The concentration of brighteners, is replenished in these regions by diffusion during a brief dwell period wherein the plating current is stopped. Next, a high current density is applied whereby the contact/vias are filled and additional copper is deposited over them at a high deposition rate. The greatest throughput benefits are realized, by way of the high current density step, when the process is applied to the formation of a dual damascene metallurgy.

대표청구항 ▼

[ What is claimed is:] [1.] A method for forming a copper plug contact to a semiconductor wafer comprising:(a) providing a semiconductor wafer;(b) depositing an insulative layer on said semiconductor wafer;(c) forming an opening in said insulative layer, thereby exposing a region of said semiconduct

[ What is claimed is:] [1.] A method for forming a copper plug contact to a semiconductor wafer comprising:(a) providing a semiconductor wafer;(b) depositing an insulative layer on said semiconductor wafer;(c) forming an opening in said insulative layer, thereby exposing a region of said semiconductor wafer;(d) forming a barrier layer on said insulative layer and within said opening;(e) depositing a copper seed layer on said barrier layer;(f) placing said wafer in an electrolyte containing copper salts and a brightener additive;(g) providing agitation of said electrolyte;(h) depositing a first layer of copper on said wafer by applying current at a first current density for a first time period;(i) discontinuing said current for a second time period while maintaining said agitation;(j) depositing a second layer of copper on said wafer by applying current at a second current density for a third time period, said third time period being sufficient to fill said opening with deposited copper; and(k) polishing the surface of said wafer to expose said insulative layer adjacent to said opening thereby forming a copper plug contact.