초록 ▼

A self-timed pipelined datapath system reduces its power dissipation by accurately controlling the active and inactive states of the multi-threshold CMOS (MT-CMOS) circuit used as its combinational circuit. The MT-CMOS circuit comprises a logic circuit of low-threshold and a power control circuit fo

A self-timed pipelined datapath system reduces its power dissipation by accurately controlling the active and inactive states of the multi-threshold CMOS (MT-CMOS) circuit used as its combinational circuit. The MT-CMOS circuit comprises a logic circuit of low-threshold and a power control circuit formed of high-threshold transistors for controlling the power feeding to the logic circuit. The self-timed pipelined datapath system comprises: a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data and a register connected to the input side of the combinational circuit; and an asynchronous signal control circuit that controls data transmission to and from each of the registers in the pipelined datapath circuit in response to a request signal. The state change of an active state to an inactive state of the combinational circuit is performed in consideration of the signal propagation time therein, whereby the issue of the request signal with respect to the combinational circuit at the preceding stage is delayed from the time the request signal with respect to the current combinational circuit is issued.

대표청구항 ▼

[ What is claimed is:] [1.] A self-timed pipelined datapath system comprising:a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data, and a register connected to the input side of said combinational circuit; and an

[ What is claimed is:] [1.] A self-timed pipelined datapath system comprising:a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data, and a register connected to the input side of said combinational circuit; and an asynchronous signal control circuit that controls data transmission to and from each of the registers in said pipelined datapath circuit in response to a request signal;wherein said combinational circuit in each of said plurality of data processing stages is composed of a multi-threshold CMOS circuit, with said multi-threshold CMOS circuit further comprisinga logic circuit portion configured by a plurality of low-threshold CMOS circuits, anda power control circuit portion, which is configured by a plurality of high-threshold MOS transistors and controls power feeding with respect to said logic circuit portion; and wherein said asynchronous signal control circuit comprises:a signal generating means for controlling active and inactive states of each of said combinational circuits in response to a request signal,and a plurality of monitoring circuits, each of which delays a write enable signal generated, in response to a request signal, to be applied to the register preceding the current combinational circuit, and issues another request signal with respect to the register succeeding the current combinational circuit.