초록 ▼

A dynamic latch receiver device comprises a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line. The device includes a first pointer signal generator for generating a sequence of one or more first pointer si

A dynamic latch receiver device comprises a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line. The device includes a first pointer signal generator for generating a sequence of one or more first pointer signals, each generated first pointer signal of a sequence corresponding to a specific latch device and overlapping in time with a prior generated first pointer signal of the sequence; and, a pulse converter device associated with a latch device for receiving a corresponding first pointer signal and generating a respective second pointer signal for input to a respective latch device, each second pointer signal generated in a non-overlapping sequence for triggering a respective latching of each data signal in synchronism with serially communicated data signals.

대표청구항 ▼

[ Having thus described our invention, what we claim as new, and desire to secure the Letters Patent is:] [1.] A dynamic latch receiver device comprising:a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line

[ Having thus described our invention, what we claim as new, and desire to secure the Letters Patent is:] [1.] A dynamic latch receiver device comprising:a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line;first pointer signal generator for generating a sequence of one or more first pointer signals, each generated first pointer signal of a sequence corresponding to a specific latch device; andpulse converter means associated with a latch device for receiving a corresponding first pointer signal and generating a respective second pointer signal for input to a respective latch device, each said second pointer signal generated in a non-overlapping sequence for triggering a respective latching of each data signal in synchronism with serially communicated data signals.