$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Methods of forming coaxial integrated circuitry interconnect lines 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/20
출원번호 US-0917449 (1997-08-22)
발명자 / 주소
  • Geusic Joseph E.
  • Ahn Kie Y.
  • Forbes Leonard
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Wells, St. John, Roberts, Gregory & Matkin, P.S.
인용정보 피인용 횟수 : 89  인용 특허 : 46

초록

Methods of forming integrated circuitry lines such as coaxial integrated circuitry interconnect lines, and related integrated circuitry are described. An inner conductive coaxial line component is formed which extends through a substrate. An outer conductive coaxial line component and coaxial dielec

대표청구항

[ What is claimed is:] [1.] A method of forming coaxial integrated circuitry interconnect lines comprising:providing an n-type semiconductive substrate having front and back surfaces;forming a masking material over one of the front and back surfaces;forming a plurality of openings into the masking m

이 특허에 인용된 특허 (46)

  1. Anthony Thomas R. (Schenectady NY), Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers.
  2. Aizawa Yoshiaki (Kanagawa-ken JPX) Katoh Toshimitu (Kanagawa-ken JPX), Bidirectional semiconductor switch.
  3. Esquivel Agerico L. (13912 Waterfall Way Dallas TX 75240) Mitchell Allan T. (2913 Green Meadow Garland TX 75042), Buried multilevel interconnect system.
  4. Hawkins Richard E. (Colchester VT), Coaxial cables.
  5. Chen Sen-Fu,TWX ; Wu Jie-Shing,TWX ; Chen Fang-Cheng,TWX ; Lee Tsung-Tser,TWX, Damage free passivation layer etching process.
  6. Anthony Thomas R. (Schenectady NY) Cline Harvey E. (Schenectady NY), Deep diode lead throughs.
  7. Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA), High performance interconnect system for an integrated circuit.
  8. Bertin Claude Louis ; Howell Wayne John ; Tonti William Robert Patrick ; Zalesnski Jerzy Maria, Integrated high-performance decoupling capacitor.
  9. Hong Gary (Hsinchu TWX), Interconnection with self-aligned via plug.
  10. Adamic ; Jr. Fred W., Inverted dielectric isolation process.
  11. Rostoker Michael D. (Boulder Creek CA) Kapoor Ashok K. (Palo Alto CA), Metal interconnect structures for use with integrated circuit devices to form integrated circuit structures.
  12. Yang Sheng-Hsing (Hsinchu TWX), Method for fabricating a bipolar power transistor.
  13. Lin Dahcheng,TWX ; Chang Jung-Ho,TWX ; Chen Hsi-Chuan,TWX, Method for fabricating a stacked, or crown shaped, capacitor structure.
  14. Chiang Chien ; Fraser David B., Method for forming multileves interconnections for semiconductor fabrication.
  15. White David M. (Sulpher Springs TX), Method for manufacturing a coaxial interconnect.
  16. Anthony Thomas R. (Schenectady NY) Houston Douglas E. (Liverpool NY) Loughran James A. (Scotia NY), Method for producing high-aspect ratio hollow diffused regions in a semiconductor body.
  17. Gaul Stephen Joseph (Melbourne FL), Method of bonding wafers having vias including conductive material.
  18. Kanber Hilda (Rolling Hills Estates CA), Method of fabricating three dimensional gallium arsenide microelectronic device.
  19. Gaul Stephen J. (Melbourne FL), Method of fabrication of surface mountable integrated circuits.
  20. Koh Wei H. (Irvine CA) McCausland Connie S. (San Juan Capistrano CA), Method of forming a microcircuit via interconnect.
  21. Soclof Sidney I. (San Gabriel CA), Method of forming lateral bipolar transistors.
  22. Gurtler Richard W. (Mesa AZ) Pearse Jeffrey (Chandler AZ) Wilson Syd R. (Phoenix AZ), Method of forming vias through two-sided substrate.
  23. Koh Wei H. ; McCausland Connie S., Microcircuit via interconnect.
  24. Mochizuki Masao (Yokohama JPX), Microwave integrated circuit (MIC) having a reactance element formed on a groove.
  25. Bass ; Jr. Roy S. (Underhill VT) Bhattacharyya Arup (Essex Junction VT) Grise Gary D. (Colchester VT), Non-volatile memory cell having Si rich silicon nitride charge trapping layer.
  26. Miles Robert S. ; Trask Philip A. ; Pillai Vincent A., Phase mask laser fabrication of fine pattern electronic interconnect structures.
  27. Havemann Robert H. (Garland TX) Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX), Porous dielectric material with a passivation layer for electronics applications.
  28. Minahan Joseph A. (Simi Valley CA) Ralph Eugene L. (San Gabriel CA) Dill Hans G. (Newhall CA), Process for fabricating a wraparound contact solar cell.
  29. Bertagnolli Emmerich,DEX ; Klose Helmut,DEX, Process for producing semiconductor components between which contact is made vertically.
  30. Finnila Ronald M. (Carlsbad CA), Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substr.
  31. Dennison Charles H. ; Doan Trung T., Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein.
  32. Roberts Martin C. (Boise ID), Semiconductor device.
  33. Koseki Osamu,JPX ; Ishii Takichi,JPX ; Mandai Masaaki,JPX ; Yoshino Tomoyuki,JPX ; Takeuchi Hitoshi,JPX, Semiconductor device having a trapezoidal joint chip.
  34. Inoue Tomotoshi (Kanagawa JPX) Terada Toshiyuki (Tokyo JPX) Tomita Kenichi (Kanagawa JPX), Semiconductor device having an improved air-bridge lead structure.
  35. Mikagi Kaoru (Tokyo JPX), Semiconductor device having an interconnection of a laminate structure and a method for manufacturing the same.
  36. Vallett David P., Semiconductor devices having backside probing capability.
  37. Tsunemine Yoshikazu (Hyogo JPX), Semiconductor memory device and manufacturing method thereof.
  38. Ichihashi Motomi,JPX, Semiconductor sensor with protective cap covering exposed conductive through-holes.
  39. Tanielian Minas H. (Bellevue WA), Silicon wafers containing conductive feedthroughs.
  40. Chang Mike F. ; Owyang King ; Hshieh Fwu-Iuan ; Ho Yueh-Se ; Dun Jowei, Surface mount and flip chip technology for total integrated circuit isolation.
  41. Gaul Stephen Joseph ; Delgado Jose Avelino, Surface mount die by handle replacement.
  42. Gaul Stephen Joseph (Melbourne FL), System for interconnecting stacked integrated circuits.
  43. Yamaga Kenichi,JPX ; Mikata Yuichi,JPX ; Yamamoto Akihito,JPX, Thermal processing method and apparatus therefor.
  44. Kato Takashi (Sagamihara JPX) Taguchi Masao (Sagamihara JPX), Three-dimensional integrated circuit and manufacturing method thereof.
  45. Bauer Friedhelm (Baden CHX) Vuilleumier Raymond (Fontainemelon CHX), Turn-off, MOS-controlled, power semiconductor component.
  46. Cronin John E. (Milton VT) Leach Michael A. (Colchester VT), VLSI coaxial wiring structure.

이 특허를 인용한 특허 (89)

  1. Lin, Chu-Fu; Kuo, Chien-Li; Yang, Ching-Li, Anti-fuse structure and programming method thereof.
  2. McDonough, Robert J.; Sun, Weimin, Apparatus and method for angled coaxial to planar structure broadband transition.
  3. Farrar, Paul A., Apparatus and method for high density multi-chip structures.
  4. Farrar, Paul A., Apparatus and method for high density multi-chip structures.
  5. Farrar, Paul A., Apparatus and method for high density multi-chip structures.
  6. McDonough,Robert J.; Sun,Weimin, Apparatus and method for inter-chip or chip-to-substrate connection with a sub-carrier.
  7. Akram, Salman; Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection.
  8. Derderian, Garo J.; Sandhu, Gurtej Singh, Atomic layer deposition and conversion.
  9. Derderian, Garo J.; Sandhu, Gurtej Singh, Atomic layer deposition and conversion.
  10. Forbes, Leonard, Capacitive techniques to reduce noise in high speed interconnections.
  11. Forbes,Leonard, Capacitive techniques to reduce noise in high speed interconnections.
  12. Lin, Yung-Chang; Kuo, Chien-Li, Capacitor structure and method of forming the same.
  13. Shacklette, Lawrence W.; Weatherspoon, Michael R.; Bruckmeyer, Joshua P.; Wilson, Arthur, Compliant high speed interconnects.
  14. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  15. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  16. Forbes, Leonard; Ahn, Kie Y., Current mode signal interconnects and CMOS amplifier.
  17. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  18. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  19. Shacklette, Lawrence W.; Weatherspoon, Michael R.; Bruckmeyer, Joshua P.; Wilson, Arthur, Digital data device interconnects.
  20. Ahn,Kie Y.; Forbes,Leonard, Electronic apparatus with deposited dielectric layers.
  21. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Electronic systems using optical waveguide interconnects formed through a semiconductor wafer.
  22. Geusic,Joseph E.; Ahn,Kie Y.; Forbes,Leonard, Electronic systems using optical waveguide interconnects formed throught a semiconductor wafer.
  23. Lin, Chin-Fu; Wu, Chun-Yuan; Liu, Chih-Chien; Tsai, Teng-Chun; Chien, Chin-Cheng, Fabrication method and structure of through silicon via.
  24. Forbes,Leonard; Eldridge,Jerome M.; Ahn,Kie Y., Full wafer silicon probe card for burn-in and testing and test system including same.
  25. Forbes, Leonard; Ahn, Kie Y., High performance silicon contact for flip chip.
  26. Forbes, Leonard; Ahn, Kie Y., High performance silicon contact for flip chip and a system using same.
  27. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  28. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  29. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  30. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  31. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  32. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  33. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  34. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability composite films to reduce noise in high speed interconnects.
  35. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability composite films to reduce noise in high speed interconnects.
  36. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability layered films to reduce noise in high speed interconnects.
  37. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability layered films to reduce noise in high speed interconnects.
  38. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability layered films to reduce noise in high speed interconnects.
  39. Akram,Salman; Ahn,Kie Y.; Forbes,Leonard, High permeability layered magnetic films to reduce noise in high speed interconnection.
  40. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability thin films and patterned thin films to reduce noise in high speed interconnections.
  41. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability thin films and patterned thin films to reduce noise in high speed interconnections.
  42. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability thin films and patterned thin films to reduce noise in high speed interconnections.
  43. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability thin films and patterned thin films to reduce noise in high speed interconnections.
  44. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability thin films and patterned thin films to reduce noise in high speed interconnections.
  45. Kie Y. Ahn, Integrated circuitry having conductive passageway interconnecting circuitry on front and back surfaces of a wafer fragment.
  46. Geusic,Joseph E.; Ahn,Kie Y.; Forbes,Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer.
  47. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same.
  48. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.
  49. Geusic,Joseph E.; Ahn,Kie Y.; Forbes,Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.
  50. Chen, Chun-Hung; Lin, Ming-Tse; Lin, Yung-Chang; Kuo, Chien-Li, Integrated structure and method for fabricating the same.
  51. Kuo, Chien-Li, Interposer structure and manufacturing method thereof.
  52. Lu, Yen-Liang; Lin, Chun-Ling; Hsu, Chi-Mao; Lin, Chin-Fu; Chen, Chun-Hung; Cheng, Tsun-Min; Tsai, Meng-Hong, Method for fabricating through-silicon via structure.
  53. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer.
  54. Kuo, Chien-Li; Lin, Yung-Chang, Method for forming semiconductor device with through silicon via.
  55. Yang, Ching-Li; Kuo, Chien-Li; Chiang, Chung-Sung; Tsai, Yu-Han; Kang, Chun-Wei, Method for forming semiconductor structure having through silicon via for signal and shielding structure.
  56. Soh, Hyongsok, Method for interconnecting arrays of micromechanical devices.
  57. Tsao, Wei-Che; Hsu, Chia-Lin; Lin, Jen-Chieh; Tsai, Teng-Chun; Hsu, Hsin-Kuo; Hsieh, Ya-Hsueh; Huang, Ren-Peng; Chen, Chih-Hsien; Lin, Wen-Chin; Hsieh, Yung-Lun, Method for manufacturing through-silicon via.
  58. Liu, Hung-Ming, Method for testing through-silicon-via (TSV) structures.
  59. Zhang, Jian-Jun; Fang, Han-Chuan; Shu, Xiao-Wei; Zhang, Jian-Dong; Liu, Yan-Jun; Zhang, Miao, Method of fabricating isolation structure.
  60. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Method of forming an optical fiber interconnect through a semiconductor wafer.
  61. Forbes, Leonard; Ahn, Kie Y., Method of forming coaxial integrated circuitry interconnect lines.
  62. Chen, Hsin-Yu; Tsai, Yu-Han; Lin, Chun-Ling; Yang, Ching-Li; Cheng, Home-Been, Method of manufacturing semiconductor structure.
  63. Ahn, Kie Y.; Forbes, Leonard, Methods for atomic-layer deposition.
  64. Farnworth,Warren M.; Collins,Dale W.; McDonald,Steven M., Methods for creating electrophoretically insulated vias in semiconductive substrates.
  65. Farnworth,Warren M.; Collins,Dale W.; McDonald,Steven M., Methods for creating electrophoretically insulated vias in semiconductive substrates.
  66. Farnworth,Warren M.; Collins,Dale W.; McDonald,Steven M., Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures.
  67. Weling, Milind; Bothra, Subhas; Gabriel, Calvin Todd; Misheloff, Michael, Methods for forming co-axial interconnect lines in a CMOS process for high speed applications.
  68. Ahn, Kie Y.; Eldridge, Jerome M.; Forbes, Leonard, Methods of fabricating full-wafer silicon probe cards for burn-in and testing of semiconductor devices.
  69. Kuo, Chien-Li; Lin, Yung-Chang; Lin, Ming-Tse, Package structure having silicon through vias connected to ground potential.
  70. Farnworth,Warren M.; Collins,Dale W.; McDonald,Steven M., Semiconductor assemblies having electrophoretically insulated vias.
  71. Kuo, Chien-Li; Lin, Yung-Chang, Semiconductor device.
  72. Kuo, Chien-Li; Lin, Yung-Chang; Lin, Ming-Tse; Wu, Kuei-Sheng; Lin, Chia-Fang, Semiconductor device having through silicon trench shielding structure surrounding RF circuit.
  73. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, Semiconductor memory device with high permeability composite films to reduce noise in high speed interconnects.
  74. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, Semiconductor memory device with high permeability lines interposed between adjacent transmission lines.
  75. Chen, Chun-Hung; Lin, Ming-Tse; Kuo, Chien-Li; Wu, Kuei-Sheng, Semiconductor structure.
  76. Li, Tzung-Lin; Wu, Chun-Chang; Tseng, Chih-Yu, Semiconductor structure and method for reducing noise therein.
  77. Farnworth,Warren M.; Collins,Dale W.; McDonald,Steven M., Semiconductor structures having electrophoretically insulated vias.
  78. Ma, Qing; Fujimoto, Harry, Silicon interposer and multi-chip-module (MCM) with through substrate vias.
  79. Kie Y. Ahn ; Leonard Forbes, Stacked integrated circuits.
  80. Lin, Chu-Fu; Lin, Ming-Tse; Lin, Yung-Chang, Substrate with integrated passive devices and method of manufacturing the same.
  81. Huang, Kuo-Hsiung; Chiou, Chun-Mao; Chen, Hsin-Yu; Tsai, Yu-Han; Yang, Ching-Li; Cheng, Home-Been, Through silicon via and method of forming the same.
  82. Huang, Kuo-Hsiung; Chiou, Chun-Mao; Chen, Hsin-Yu; Tsai, Yu-Han; Yang, Ching-Li; Cheng, Home-Been, Through silicon via and method of forming the same.
  83. Kuo, Chien-Li; Chen, Chun-Hung; Lin, Ming-Tse; Lin, Yung-Chang, Through silicon via and process thereof.
  84. Chen, Hsin-Yu; Cheng, Home-Been; Tsai, Yu-Han; Yang, Ching-Li, Through silicon via structure.
  85. Chen, Hsin-Yu; Cheng, Home-Been; Tsai, Yu-Han; Yang, Ching-Li, Through silicon via structure and method of fabricating the same.
  86. Tsai, Teng-Chun; Wu, Chun-Yuan; Lin, Chin-Fu; Liu, Chih-Chien; Chien, Chin-Cheng, Through-silicon via forming method.
  87. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
  88. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
  89. Forbes,Leonard; Cloud,Eugene H.; Ahn,Kie Y., Transmission lines for CMOS integrated circuits.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로