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Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0868332 (1997-06-03)
발명자 / 주소
  • Wetzel Jeffrey Thomas
출원인 / 주소
  • Motorola Inc.
인용정보 피인용 횟수 : 151  인용 특허 : 4

초록

A method for forming a dual inlaid contact structure (damascene) begins by etching dual inlaid contact structures (32, 34, and 36). Masking layers (28) are (228) and the deposition of low-K dielectric material 26 is used to selectively form low-K regions (30) only in critical areas where low-K diele

대표청구항

[ What is claimed is:] [1.] A method for forming an integrated circuit structure, the method comprising the steps of:forming a first dielectric region wherein the first dielectric region is patterned to have an opening having a first sidewall opposite a second sidewall, the first dielectric region c

이 특허에 인용된 특허 (4)

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