초록 ▼

A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with

A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with a dielectric material having a low dielectric constant. In another embodiment, a conformal dielectric coating is deposited, having a low dielectric constant.

대표청구항 ▼

[ What is claimed is:] [1.] A method of manufacturing a semiconductor device, which method comprises sequentially:depositing a plurality of dielectric and conductive layers sequentially formed on one another above a semiconductor substrate wherein each dielectric layer comprises a first dielectric m

[ What is claimed is:] [1.] A method of manufacturing a semiconductor device, which method comprises sequentially:depositing a plurality of dielectric and conductive layers sequentially formed on one another above a semiconductor substrate wherein each dielectric layer comprises a first dielectric material and each conductive layer comprises at least one conductive pattern;removing sections of each dielectric layer leaving only a portion of the first dielectric material substantially under each conductive pattern of the conductive layer thereon; anddepositing a first conformal dielectric coating thereon, rein each dielectric layer comprises air spaces between and adjoining each portion of the first dielectric material having the first conformal dielectric coating thereon and each conductive level comprises a plurality of conductive patterns separated by air spaces.