초록 ▼

A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed ha

A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, a digital control signal is disclosed to control the overall capacitance for the discretely variable capacitance circuit, and a variable control signal is disclosed to control an overall capacitance for the continuously variable capacitance circuit. In addition, the output frequency may be varied by adjusting either the digital control word or the variable control word.

대표청구항 ▼

[ We claim:] [1.] A frequency synthesizer having at least one variable frequency output, the output frequency varying as a capacitance within the synthesizer varies, comprising:a differential amplifier having a positive side voltage node and negative side voltage node;a positive side discretely vari

[ We claim:] [1.] A frequency synthesizer having at least one variable frequency output, the output frequency varying as a capacitance within the synthesizer varies, comprising:a differential amplifier having a positive side voltage node and negative side voltage node;a positive side discretely variable capacitance circuit including a plurality of capacitor circuits;a negative side discretely variable capacitance circuit including a plurality of capacitor circuits paired with the capacitor circuits in the positive side discretely variable capacitance circuit;wherein the paired capacitor circuits comprise:a positive side capacitor circuit coupled to the positive side voltage node;a positive side switch circuit coupled to the positive side voltage node;a negative side capacitor circuit coupled to the negative side voltage node;a negative side switch circuit coupled to the negative side voltage node; andan additional switch circuit coupled between the positive side and negative side circuits to reduce an overall switch resistance when the negative side switch circuit and the positive side switch are in a conductive state; andwherein the positive and negative side switch circuits selectively include the positive and negative side capacitor circuits within the overall capacitance for the discretely variable capacitance circuit depending upon at least one control signal applied to the positive and negative side switch circuits.