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Optional on chip power supply bypass capacitor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01G-040/02
  • H01G-004/30
출원번호 US-0946555 (1997-10-07)
발명자 / 주소
  • Worley Eugene Robert
  • Mann Richard Arthur
출원인 / 주소
  • W.
  • E. R.
인용정보 피인용 횟수 : 53  인용 특허 : 14

초록

An integrated circuit includes main power busses located on the next to the top most level of metal and a top level of metal separated from the main power busses by a thin dielectric. The top most level metal is connected to one of the power buses either through bond wires or through contacts. This

대표청구항

[ What is claimed is:] [1.] A semiconductor integrated circuit comprising:a semiconductor substrate;circuits formed on said substrate;power rails and ground rails formed on said substrate, each of said rails being used to supply power for said circuits and said rails being formed on a top most inter

이 특허에 인용된 특허 (14)

  1. Kelso John F. (Apollo PA), Alumina multilayer wiring substrate provided with high dielectric material layer.
  2. Roberts Ceredig ; Srinivasan Anand ; Sandhu Gurtej ; Sharan Sujit, Facet etch for improved step coverage of integrated circuit contacts.
  3. Wakabayashi Tetsushi (Yokohama JPX) Muratake Kiyoshi (Kawasaki JPX), Integrated circuit device having package with bypass capacitor.
  4. Patel Bharat D. (San Jose CA) Tam Stephen Y. (San Francisco CA) Shah Pravin R. (Sunnyvale CA), Integrated circuit structure having compensating means for self-inductance effects.
  5. Lynch Brian J. (Milpitas CA), Integrated circuit with on-chip ground plane.
  6. Gonzalez Fernando (Boise ID), Low-profile, folded-plate dram-cell capacitor fabricated with two mask steps.
  7. Hayano Kiminori (Tokyo JPX), MOS type semiconductor device potential stabilizing circuit with series MOS capacitors.
  8. Malladi Deviprasad (Campbell CA) Ansari Shahid S. (Milpitas CA) Bogatin Eric (San Jose CA), Method for direct attachment of an on-chip bypass capacitor in an integrated circuit.
  9. Malladi Deviprasad ; Ansari Shahid S. ; Bogatin Eric, Method for direct attachment of an on-chip bypass capacitor in an integrated circuit.
  10. Kwon Kee-Won,KRX ; Kang Chang-Seok,KRX, Method for manufacturing a semiconductor device having a ferroelectric capacitor.
  11. Loh Wah K. (Richardson TX), Packaged integrated circuit with encapsulated electronic devices.
  12. Suzuki Kazumasa (Tokyo JPX), Power supply wiring for semiconductor device.
  13. Shiba Hiroshi (Tokyo JPX) Mikoshiba Hiroaki (Tokyo JPX), Semiconductor integrated circuit having a capacitor for stabilizing a voltage at a power supplying wiring.
  14. Chou William T. (Cupertino CA) Peters Michael G. (Santa Clara CA) Wang Wen-chou Vincent (Cupertino CA) Wheeler Richard L. (San Jose CA), Substrate with thin film capacitor and insulating plug.

이 특허를 인용한 특허 (53)

  1. Hsu, Jimmy, Bonding pad design for impedance matching improvement.
  2. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
  3. Leydier, Robert; Bonvalot, Beatrice; Servel, Eric, Device with integrated circuit made secure by attenuation of electric signatures.
  4. Chen, Shui-Hung; Lee, Jian-Hsing; Shih, Jiaw-Ren, Extended length metal line for improved ESD performance.
  5. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  6. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  7. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  8. Segan, Scott A.; Van Horn, Scott T.; Hall, Gary E.; Gehman, Matthew J.; Muscavage, Richard, Integrated circuit power grid with improved routing resources and bypass capacitance.
  9. Cathelin,Andr챕a; Bernard,Christophe; Delpech,Philippe; Troadec,Pierre; Salager,Laurent; Garnier,Christophe, Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen.
  10. Williams,Richard K.; Cornell,Michael E.; Chan,Wai Tien, Manufacturing and testing of electrostatic discharge protection circuits.
  11. Jiang, Tongbi; Wu, Zhiqiang, Method and apparatus for reducing substrate bias voltage drop.
  12. Jiang,Tongbi; Wu,Zhiqiang, Method and apparatus for reducing substrate bias voltage drop.
  13. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  14. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  15. Sabin, Gregory D.; Gross, William J.; Chang, Jung-Yueh, Method for placing active circuits beneath active bonding pads.
  16. Weaver,Kevin; Acedo,Henry; Durbha,Lakshmi, Method of editing a semiconductor die.
  17. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  18. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  19. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  20. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  21. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  22. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  23. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  24. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  26. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  27. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  28. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  29. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  30. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  32. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  33. Kawamoto,Atsunobu, Power semiconductor device.
  34. Belleville, Marc; Bruel, Michel, SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit.
  35. Takabayashi, Yasutaka; Morimoto, Masashi, Semiconductor IC with an inside capacitor for a power supply circuit and a method of automatically designing the same.
  36. Ishikawa, Hirotaka, Semiconductor apparatus including bypass capacitor having structure for making automatic design easy, and semiconductor apparatus layout method.
  37. Oyamada, Seisei, Semiconductor device and bypass capacitor module.
  38. Taya, Masatoshi; Ohno, Takio; Murata, Naofumi, Semiconductor device having improved trench structure.
  39. Sekimoto,Yasuhiko, Semiconductor device with bypass capacitor.
  40. Rashed, Mahbub; Doman, David; Tarabbia, Marc; Lin, Irene; Kim, Jeff; Nguyen, Chinh; Soss, Steve; Johnson, Scott; Kengeri, Subramani; Venkatesan, Suresh, Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same.
  41. Weaver,Kevin; Acedo,Henry; Durbha,Lakshmi, Semiconductor die with an editing structure.
  42. Sano, Fumihiko, Semiconductor integrated circuit device and method of manufacturing the same.
  43. Wu, Cheng-Tsung; Lin, Shin-Cheng; Ho, Yu-Hao; Lin, Wen-Hsin, Semiconductor structure having conductive layer overlapping field oxide.
  44. Williams,Richard K.; Cornell,Michael E.; Chan,Wai Tien, Testable electrostatic discharge protection circuits.
  45. Kong,Weiran; Ho,Bernard; Greenhill,David; Bobba,Sudhakar, Thin capacitive structure.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Fazelpour, Siamak, Transformer comprising stacked inductors.
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