초록 ▼

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embo

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-EISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches the bridge interface from the bridge or PCI bus, and it is recognized that the address is within the range, then the fast burst mode is allowed, and write addresses are allowed to follow one another without the delay for the snoop phase or the possibility of defer or retry.

대표청구항 ▼

[ What is claimed is:] [1.] A computer system comprising:a processor including at least one internal cache memory;a system bus coupled to the processor;a main memory coupled to the system bus;an expansion bus;a bridge circuit coupled between the system bus and the expansion bus;a mass storage device

[ What is claimed is:] [1.] A computer system comprising:a processor including at least one internal cache memory;a system bus coupled to the processor;a main memory coupled to the system bus;an expansion bus;a bridge circuit coupled between the system bus and the expansion bus;a mass storage device controller coupled to the expansion bus; anda mass storage device coupled to the mass storage device controller;wherein the processor is operable to initiate transactions on the system bus directed to the mass storage device controller and also to initiate transactions on the system bus directed to the main memory;wherein the transactions directed to the mass storage device controller are initiated by a request being applied to the system bus followed by a snoop phase; andwherein transactions directed to a defined range of main memory addresses are not deferred or retried and are implemented without waiting for a snoop phase.