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Copper stud structure with refractory metal liner 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/485
출원번호 US-0941857 (1997-09-30)
발명자 / 주소
  • Harper James M. E.
  • Geffken Robert M.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    DeLio & Peterson LLCTomaszewski
인용정보 피인용 횟수 : 39  인용 특허 : 13

초록

A multilayer interconnected electronic component having increased electromigration lifetime is provided. The interconnections are in the form of studs and comprise vertical side walls having a refractory metal diffusion barrier liner along the sidewalls. The stud does not have a barrier layer at the

대표청구항

[ Thus, having described the invention, what is claimed is:] [1.] A damascene or dual damascene interconnect structure in a multilayer electronic component for connecting metallization on one layer to a trench or via extending to said metallization the electronic component having an enhanced electro

이 특허에 인용된 특허 (13)

  1. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
  2. Crank Sue E. (Coppell TX), Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer.
  3. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  4. Kim Jun K. (Seoul KRX) Lee Kyung I. (Seoul KRX), Method for forming a copper metal wiring with aluminum containing oxidation barrier.
  5. Anantha Narasipur G. (Hopewell Junction NY) Bhatia Harsaran S. (Wappingers Falls NY) Gaur Santosh P. (Wappingers Falls NY) Mauer ; IV John L. (South Kent CT), Method for making Schottky diode having limited area self-aligned guard ring.
  6. Nagashima Naoki (Kanagawa JPX), Method of forming multilayer interconnection structure.
  7. Shoda Naohiro (Wappingers Falls NY), Method of forming studs and interconnects in a multi-layered semiconductor device.
  8. Colgan Evan G. (Wappingers Falls NY) Fryer Peter M. (Mamaroneck NY), Method of making Alpha-Ta thin films.
  9. Inohara Masahiro,JPX ; Shibata Hideki,JPX ; Matsuno Tadashi,JPX, Method of making semiconductor apparatus having wiring groove and contact hole formed in a self-alignment manner.
  10. Page Allen (San Antonio TX) Sayka Anthony (San Antonio TX), Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric.
  11. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
  12. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
  13. Geffken Robert M. (Burlington VT) Rutten Matthew J. (Milton VT), Transverse diffusion barrier interconnect structure.

이 특허를 인용한 특허 (39)

  1. Cho, Chih-Chen, Backend metallization method and device obtained therefrom.
  2. Cho,Chih Chen, Backend metallization method and device obtained therefrom.
  3. Amit P. Marathe ; Pin-Chin Connie Wang ; Christy Mei-Chu Woo, Conductor reservoir volume for integrated circuit interconnects.
  4. Shamble, Edward M.; Boonstra, Thomas; Brownell, David J.; Crow, David A., Contact monitor, method of forming same and method of analizing contact-, via- and/or trench-forming processes in an integrated circuit.
  5. Hussein,Makarem A., Continuous metal interconnects.
  6. Learn, Arthur J.; Sherman, Steven R.; Geffken, Robert Michael; Hautala, John J., Copper interconnect wiring and method and apparatus for forming thereof.
  7. Geffken,Robert M.; Hautala,John J.; Sherman,Steven R.; Learn,Arthur J., Copper interconnect wiring and method of forming thereof.
  8. Dawn M. Hopper ; Minh Van Ngo ; Joffre F. Bernard, Dielectric treatment in integrated circuit interconnects.
  9. You, Lu; Wang, Fei; Woo, Christy, Dual damascene integration scheme for preventing copper contamination of dielectric layer.
  10. You, Lu; Wang, Fei; Woo, Christy, Dual damascene integration scheme for preventing copper contamination of dielectric layer.
  11. Geffken, Robert M.; Hautala, John J., Dual damascene integration structure and method for forming improved dual damascene integration structure.
  12. Gealy, Dan; Bhat, Vishwanath; Srividya, Cancheepuram V.; Rocklein, M. Noel, Graded dielectric layers.
  13. Gealy, Dan; Bhat, Vishwanath; Srividya, Cancheepuram V.; Rocklein, M. Noel, Graded dielectric structures.
  14. Gealy, F. Daniel; Bhat, Vishwanath; Srividya, Cancheepuram V.; Rocklein, M. Noel, Graded dielectric structures.
  15. Asai,Koyu; Tobimatsu,Hiroshi; Kawata,Hiroyuki; Sawada,Mahito, Interconnection structure of semiconductor device.
  16. Asai,Koyu; Tobimatsu,Hiroshi; Kawata,Hiroyuki; Sawada,Mahito, Interconnection structure of semiconductor device.
  17. Aubel, Oliver; Hasse, Wolfgang; Hommel, Martina; Koerner, Heinrich, Long-term heat-treated integrated circuit arrangements and methods for producing the same.
  18. Chine-Gie Lou TW, Method for forming a via and interconnect in dual damascene.
  19. Marathe, Amit P.; Wang, Pin-Chin Connie; Woo, Christy Mei-Chu, Method for forming conductor reservoir volume for integrated circuit interconnects.
  20. Oyamatsu, Hisato, Method for manufacturing multilayer wiring structure semiconductor device.
  21. Woo, Christy Mei-Chu; Pangrle, Suzette K.; Ngo, Minh Van, Method of forming low resistance barrier on low k interconnect.
  22. Woo, Christy Mei-Chu; Pangrle, Suzette K.; Wang, Connie Pin-Chin, Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer.
  23. Fan, Chih-Peng; Chia, Yen-Ti, Method of making a circuit structure.
  24. Mei-Sheng Zhou SG; Simon Chooi SG; Yi Xu SG, Method to form damascene interconnects with sidewall passivation to protect organic dielectrics.
  25. Wojtczuk, Steven J.; Moe, James G.; Little, Roger G., Nanophotovoltaic devices.
  26. Christy Mei-Chu Woo ; Minh Quoc Tran, Pre-fill CMP and electroplating method for integrated circuits.
  27. Lopatin, Sergey D.; Wang, Pin-Chin Connie, Seedless barrier layers in integrated circuits and a method of manufacture therefor.
  28. Boyanov, Boyan, Self-enclosed asymmetric interconnect structures.
  29. Park, Ki-Chul; Choi, Seung-Man, Semiconductor device having multi-layer copper line and method of forming same.
  30. Park, Ki-Chul; Choi, Seung-Man, Semiconductor device having multi-layer copper line and method of forming the same.
  31. Naoteru Matsubara JP, Semiconductor device having silicon oxide sidewalls.
  32. Komada, Daisuke, Semiconductor device manufacturing method.
  33. Higashi, Kazuyuki; Takase, Tamao; Shibata, Hideki, Semiconductor device manufacturing method including forming step of SOI structure and semiconductor device having SOI structure.
  34. Boyanov, Boyan; Singh, Kanwal Jit; Clarke, James; Myers, Alan, Semiconductor interconnect structures.
  35. Dallmann, Gerald; Meinhold, Dirk; Vater, Alfred, Semiconductor structure and method for making same.
  36. Meinhold, Dirk; Dallmann, Gerald; Vater, Alfred, Semiconductor structure and method for making same.
  37. Vassili Kitch, Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures.
  38. Farrar, Paul A., Structures and methods to enhance copper metallization.
  39. Woo, Christy Mei-Chu; Wang, Pin-Chin Connie; Marathe, Amit P., Via formation in integrated circuit interconnects.
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