이 특허를 인용한 특허 (54)

1. Weimer, Ronald A.; Gonzalez, Fernando, Ammonia gas passivation on nitride encapsulated devices.

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2. Hopper, Peter J.; Johnson, Peter; Hwang, Kyuwoon; Mian, Michael; Drury, Robert, Conductive trace with reduced RF impedance resulting from the skin effect.

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3. Knuepfer, Bernhard, Die and chip.

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4. Ohsaka, Shigeo; Domoto, Shinichi; Okada, Nobumasa, Electrode structure, process for fabricating electrode structure and semiconductor light-emitting device.

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5. Weimer, Ronald A.; Gonzalez, Fernando, Gas passivation on nitride encapsulated devices.

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6. Kloen Hendrik K.,NLX ; Huiskamp Lodewijk P.,NLX, Integrated circuit device.

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7. Weimer, Ronald A., Integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source.

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8. Yau, Wai-Fan; Cheung, David; Jeng, Shin-Puu; Liu, Kuowei; Yu, Yung-Cheng, Low dielectric constant film produced from silicon compounds comprising silicon-carbon bond.

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9. Chuang, Chita; Chuang, Yao-Chun; Chen, Chih-Hua; Kuo, Chen-Cheng; Chen, Chen-Shien, Metal routing architecture for integrated circuits.

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10. Kuo, Chen-Cheng; Chuang, Chita; Chen, Chih-Hua; Chen, Chen-Shien; Chuang, Yao-Chun, Metal routing architecture for integrated circuits.

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11. Lee,Jin Hyuk; Kim,Gu Sung; Lee,Dong Ho; Jang,Dong Hyeon, Method for manufacturing a wafer level chip scale package.

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12. Sabin, Gregory D.; Gross, William J.; Chang, Jung-Yueh, Method for placing active circuits beneath active bonding pads.

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13. Weimer, Ronald A., Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source.

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14. Weimer, Ronald A., Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source.

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15. Hopper,Peter J.; Johnson,Peter; Hwang,Kyuwoon; Mian,Michael; Drury,Robert, Method of forming a dual damascene metal trace with reduced RF impedance resulting from the skin effect.

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16. Hopper,Peter J.; Johnson,Peter; Hwang,Kyuwoon; Mian,Michael; Drury,Robert, Method of forming a metal trace with reduced RF impedance resulting from the skin effect.

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17. Hopper,Peter J.; Johnson,Peter; Hwang,Kyuwoon; Mian,Michael; Drury,Robert, Method of forming an etched metal trace with reduced RF impedance resulting from the skin effect.

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18. Sugimoto, Yasutaka, Multilayer ceramic substrate, method for producing same, and electronic component.

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19. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.

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20. James George Michael ; Jeffrey Scott Miller ; Gary Dale Pittman ; Rosemary Ann Previti-Kelly, Post-processing a completed semiconductor device.

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21. Weimer,Ronald A., Process of forming an electrically erasable programmable read only memory with an oxide layer exposed to hydrogen and nitrogen.

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22. Anthony K. Stamper ; Sally J. Yankee, Recessed bond pad.

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23. Anthony K. Stamper ; Sally J. Yankee, Recessed bond pad.

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24. Stamper, Anthony K.; Yankee, Sally J., Recessed bond pad.

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25. Zhang, Tianhong; Ditali, Akram, Semiconductor constructions.

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26. Zhang, Tianhong; Ditali, Akram, Semiconductor constructions, semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers.

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27. Sakihama, Kazuhisa; Yamaguchi, Akira, Semiconductor device.

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28. Naoto Akiyama JP, Semiconductor device and method for manufacturing same.

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29. Nakamura,Hiroki, Semiconductor device having wiring patterns and dummy patterns covered with insulating layer.

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30. Yuzawa, Takeshi; Yuzawa, Hideki; Takano, Michiyoshi, Semiconductor device that improves electrical connection reliability.

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31. Wu, Hui-Min; Lan, Bang-Chiang; Wang, Ming-I; Su, Tzung-I; Huang, Chien-Hsin; Su, Chao-An; Tan, Tzung-Han; Chen, Min; Lin, Meng-Jia, Semiconductor structure, pad structure and protection structure.

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32. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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33. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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34. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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35. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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36. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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37. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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38. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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39. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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40. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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41. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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42. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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43. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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44. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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45. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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46. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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47. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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48. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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49. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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50. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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51. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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52. Fried, David Michael; Hergenrother, John Michael; McNab, Sharee Jane; Rooks, Michael J.; Topol, Anna, Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels.

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53. Chen, Wei-Yu; Chen, Hsien-Wei; Su, An-Jhih; Hsieh, Cheng-Hsien, Under bump metallurgy (UBM) and methods of forming same.

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54. Chen, Wei-Yu; Chen, Hsien-Wei; Su, An-Jhih; Hsieh, Cheng-Hsien, Under bump metallurgy (UBM) and methods of forming same.

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