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Component carrier with raised bonding sites 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/11
  • H01L-023/48
  • H01L-029/62
  • H01L-029/40
  • H01L-023/52
출원번호 US-0088834 (1998-06-02)
발명자 / 주소
  • Feilchenfeld Natalie Barbara
  • Fuerniss Stephen Joseph
  • Gaynes Michael Anthony
  • Pierson Mark Vincent
  • Hoontrakul Pat
출원인 / 주소
  • International Business Machines Corp.
대리인 / 주소
    Pivnichny
인용정보 피인용 횟수 : 34  인용 특허 : 26

초록

Chip carrier packages, integrated circuits, wiring boards, and assemblies in computer systems are made having conductive adhesive interconnections. Electrically conductive polymer paste with metal particles and powders are used with photoimagable polymer films to form the interconnection structure.

대표청구항

[ What is claimed is:] [1.] A component carrier having raised bonding sites of connected joining material, comprising:a substrate having one or more electrically conductive wiring layers, said layers having conductive lines terminating in connecting pad areas;a first layer of cured electrically cond

이 특허에 인용된 특허 (26)

  1. Patil Sadanand R. (San Jose CA) Chou Tai-Yu (Pleasonton CA) Chakrabarti Prabhansu (Sunnyvale CA), Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device packa.
  2. Chi Tom Y. (San Gabriel CA) Raymond Brook D. (Hermosa Beach CA), Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal nitride barrier layer t.
  3. Kamperman James Steven ; Gall Thomas Patrick ; Stone David Brian, Cap providing flat surface for DCA and solder ball attach and for sealing plated through holes, multi-layer electronic.
  4. Tomura Yoshihiro (Hirakata JPX) Bessho Yoshihiro (Higashiosaka JPX) Hakotani Yasuhiko (Nishinomiya JPX), Chip package, a chip carrier, a terminal electrode for a circuit substrate and a chip package-mounted complex.
  5. Andros Frank E. (Binghamton NY) Angulas Christopher G. (Owego NY) Milewski Joseph M. (Binghamton NY), Electronic package structure and method of making same.
  6. Morrison Paul-David (Round Rock TX), Hermetic semiconductor device having jumper leads.
  7. Marcantonio Gabriel (Nepean CAX), Integrated circuit chip package.
  8. Swamy Deepak (Austin TX), Mechanical printed circuit board and ball grid array interconnect apparatus.
  9. Neftin Shimon (Kiriat Shmona ILX), Method of manufacturing a composite structure for use in electronic devices and structure, manufactured by said method.
  10. Rostoker Michael D. (San Jose CA), Multi-chip semiconductor arrangements using flip chip dies.
  11. Bhansali Ameet ; Zhu Qing, Multi-layer C4 flip-chip substrate.
  12. Kuramochi Toshiyuki (Kawasaki JPX), Multichip-module having an HDI and a temporary supporting substrate.
  13. Yamamoto Hiroaki (Osaka JPX) Nishino Seiji (Osaka JPX) Yamamoto Kazuhisa (Osaka JPX), Optical element and method of fabricating the same.
  14. Hirakawa Tetsuo (Kokubu JPX) Matsukawa Kozo (Kokubu JPX), Package for a semiconductor element.
  15. Beddingfield Stanley C. ; Higgins ; III Leo M. ; Gentile John C., Process for underfilling a flip-chip semiconductor device.
  16. Arima Hideo (Yokohama JPX) Takeda Kenji (Kamakura JPX) Yamamura Hideho (Yokohama JPX) Kobayashi Fumiyuki (Sagamihara JPX), Semiconductor chip carrier, module having same chip carrier mounted therein, and electronic device incorporating same mo.
  17. Stager Mark P. ; Yee Abraham F. ; Padmanabhan Gobi R., Semiconductor chip package with interconnect layers and routing and testing methods.
  18. Yamashita Chikara,JPX, Semiconductor device having a perforated base film sheet.
  19. Wenzel James F. (Austin TX) Chopra Mona A. (Austin TX) Foster Stephen W. (Dripping Springs TX), Semiconductor device having built-in high frequency bypass capacitor.
  20. Uda Takayuki (Ohme JPX) Hiramoto Toshiro (Ohme JPX) Tamba Nobuo (Ohme JPX) Ishida Hisashi (Higashiyamato JPX) Akimoto Kazuhiro (Akishima JPX) Odaka Masanori (Kodaira JPX) Tanaka Tasuku (Hamura JPX) H, Semiconductor integrated circuit device and methods for production thereof.
  21. Harada Takashi (Hidaka JPX) Yoshihara Kazuhiro (Ohme JPX) Masuzawa Kazutaka (Ueda JPX) Hayashi Kiyoshi (Ohme JPX) Kumazawa Jun (Ohme JPX) Nagai Kenji (Iruma JPX) Nishiuma Masahiko (Ohme JPX) Kamada C, Semiconductor integrated device having parallel signal lines.
  22. Arima Hideo (Yokohama JPX) Matsui Kiyoshi (Yokohama JPX) Takeda Kenji (Kamakura JPX), Semiconductor package employing substrate assembly having a pair of thin film circuits disposed one on each of oppositel.
  23. Iwasaki Hiroshi,JPX, Seminconductor package.
  24. Lin Paul T. (Austin TX), Shielded liquid encapsulated semiconductor device and method for making the same.
  25. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX), Thermally enhanced semiconductor device having exposed backside and method for making the same.
  26. Higgins ; III Leo M. (Austin TX), Z-axis compliant mechanical IC wiring substrate and method for making the same.

이 특허를 인용한 특허 (34)

  1. Masao Takeuchi JP; Yoshiharu Fujimori JP; Chuji Tomita JP, Cream solder apparatus and printing method therefor.
  2. Honda, Kazuyoshi; Echigo, Noriyasu; Odagiri, Masaru; Sunagare, Nobuki; Suzawa, Shinichi, Layered product, capacitor and a method for producing the layered product.
  3. Honda, Kazuyoshi; Echigo, Noriyasu; Odagiri, Masaru; Sunagare, Nobuki; Suzawa, Shinichi, Layered product, capacitor and a method for producing the layered product.
  4. Pierson, Mark Vincent, Method for forming solder connections on a circuitized substrate.
  5. Robert, Brian Joseph, Multi-component power structures and methods for forming the same.
  6. Rajashekara, Kaushik; Wang, Ruxi; Chen, Zheng; Boroyevich, Dushan, Multilayer packaged semiconductor device and method of packaging.
  7. Minami, Toshiaki; Sakuta, Toshiyuki; Kuwata, Makoto, Semiconductor device.
  8. Minami,Toshiaki; Sakuta,Toshiyuki; Kuwata,Makoto, Semiconductor device.
  9. Farnworth, Warren M.; Wood, Alan G.; Wark, James M.; Hembree, David R.; Ahmad, Syed Sajid; Hess, Michael E.; Jacobson, John O., Semiconductor devices with permanent polymer stencil and method for manufacturing the same.
  10. Farnworth,Warren M.; Wood,Alan G.; Wark,James M.; Hembree,David R.; Ahmad,Syed Sajid; Hess,Michael E.; Jacobson,John O., Semiconductor devices with permanent polymer stencil and method for manufacturing the same.
  11. Imai,Takahiro, Stacked semiconductor chips.
  12. Van Keymeulen, Bjorn; Bossuyt, Frederick; Vervust, Thomas, Textile integration of electronic circuits.
  13. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  14. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  15. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  16. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  17. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  18. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  19. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  20. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  21. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  22. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  23. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  24. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  25. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  26. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  27. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  28. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  29. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  30. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  31. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  32. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  33. Standing, Martin, Wafer level underfill and interconnect process.
  34. Standing, Martin, Wafer level underfill and interconnect process.
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