초록 ▼

A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen p

A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen programmable elements) of the array. In one embodiment, a separate read bit line is provided to facilitate faster read operations. A sixteen-to-one multiplexer/demultiplexer circuit is used to pass selected bit values to an output terminal. The array of programmable elements is programmable both from configuration lines during a configuration mode, and by data transmitted on the interconnect resources through the multiplexer/demultiplexer circuit. In one embodiment, the programmable elements of the array are connected in pairs to product term generation circuitry. Product terms generated by the product term circuitry are passed to a macrocell circuit to perform programmable array logic (PAL) logic operations. In another embodiment, a CLB includes four LMCs and a multiplier circuit such that large amounts of logic are locally implemented, thereby avoiding signal delays associated with transmission over general purpose interconnect resources within a PLD.

대표청구항 ▼

[ We claim:] [1.] A programmable logic device including a plurality of configurable logic blocks and interconnect resources for transmitting signals to the configurable logic blocks, each configurable logic block including a logic/memory circuit comprising:a first plurality of input terminals for re

[ We claim:] [1.] A programmable logic device including a plurality of configurable logic blocks and interconnect resources for transmitting signals to the configurable logic blocks, each configurable logic block including a logic/memory circuit comprising:a first plurality of input terminals for receiving a first set of input signals from the interconnect resources;a decoder for generating address signals in response to the first plurality of input signals;an array including programmable elements for storing a plurality of bit values, word lines connected to the decoder for receiving the address signals, and bit lines for transmitting bit values to the programmable elements in response to the address signals;an input control circuit connected to the first plurality of input terminals for selectively transmitting the first set of input signals onto a group of the bit lines; anda product term circuit for generating a plurality of product terms in response to the first set of input signals transmitted on the group of the bit lines and the bit values stored in the programmable elements.