|국가/구분||United States(US) Patent 등록|
|미국특허분류(USC)||326/039 ; 326/041 ; 326/038|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 250 인용 특허 : 6|
A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen programmable elements) of the array. In one embodiment, a separate read bit line is provided to facilitate faster read operations. A sixteen-to-one multiplexer/demultiplexer circuit is used to pass selected bit values to an output terminal. The array of program...
[ We claim:] [1.] A programmable logic device including a plurality of configurable logic blocks and interconnect resources for transmitting signals to the configurable logic blocks, each configurable logic block including a logic/memory circuit comprising:a first plurality of input terminals for receiving a first set of input signals from the interconnect resources;a decoder for generating address signals in response to the first plurality of input signals;an array including programmable elements for storing a plurality of bit values, word lines connect...