$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Salicide formation on narrow poly lines by pulling back of spacer

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/336
출원번호 US-0188522 (1998-11-09)
발명자 / 주소
  • Pey Kin-Leong,SGX
  • Siah Soh-Yun,SGX
출원인 / 주소
  • Chartered Semiconductor Manufacturing Ltd., SGX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 63  인용 특허 : 14

초록

A method for a salicide process where S/D silicide contacts are formed in a separate silicide step than the gate silicide contacts. Preferably, TiSi.sub.2 is formed on S/D regions and TiSi.sub.2 or CoSi.sub.2 is formed on Poly electrodes (lines or gates) by etching back a sidewall spacer on the poly

대표청구항

[ What is claimed is:] [1.] A method for fabricating field effect transistors having low sheet resistance gate electrodes comprising the steps of:a) providing a substrate;b) forming shallow trench isolation regions surrounding and electrically isolating device areas;c) forming a gate oxide layer on

이 특허에 인용된 특허 (14)

  1. Ho Chaw Sing,SGX ; Karunasiri R. P. G.,SGX ; Chua Soo Jin,SGX ; Pey Kin Leong,SGX ; Lee Kong Hean,SGX, Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices.
  2. Doyle Brian ; Bai Gang, Low resistance gate electrode layer and method of making same.
  3. Kuroda Hideaki,JPX, MOS transistor and fabrication process for the same.
  4. Wu Shye-Lin,TWX, Method of fabricating a short-channel MOS device.
  5. Nasr Andre I. (Marlboro MA), Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer.
  6. Wright Peter J., Method of forming low resistance gate electrodes.
  7. Wong Harianto,SGX ; Pey Kin Leong,SGX ; Chan Lap, Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance.
  8. Chiu Tzu-Yin (Martinsville NJ) Erceg Frank M. (Bethlehem PA) Krafty Francis A. (Bangor PA) Liu Te-Yin M. (Hsin-Chu PA TWX) Possanza William A. (Northampton PA) Sung Janmye (Warren NJ), Process for manufacturing semiconductor BICMOS device.
  9. Chang A. J.,TWX ; Chu Chih-Hsun,TWX, Process for manufacturing semiconductor devices having raised doped regions.
  10. Chen Tung-Po,TWX ; Pan Hong-Tsz,TWX ; Hsieh Wen-Yi,TWX, Salicide formation process.
  11. Kao Dah-Bin (Palo Alto CA) Pierce John (Palo Alto CA), Self-aligned polycide process that utilizes a planarized layer of material to expose polysilicon structures to a subsequ.
  12. Xiang Qi ; Pramanick Shekhar ; Lin Ming-Ren, Self-aligned silicide gate technology for advanced submicron MOS devices.
  13. O'Brien Sean ; Prinslow Douglas A., Self-aligned silicide process.
  14. Huang Jenn Ming,TWX, Silicide and salicide on the same chip.

이 특허를 인용한 특허 (63)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  2. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  3. Amos,Ricky S.; Boyd,Diane C.; Cabral, Jr.,Cyril; Kaplan,Richard D.; Kedzierski,Jakub T.; Ku,Victor; Lee,Woo Hyeong; Li,Ying; Mocuta,Anda C.; Narayanan,Vijay; Steegen,An L.; Surendra,Maheswaran, CMOS silicide metal gate integration.
  4. Amos,Ricky S.; Boyd,Diane C.; Cabral, Jr.,Cyril; Kaplan,Richard D.; Kedzierski,Jakub T.; Ku,Victor; Lee,Woo Hyeong; Li,Ying; Mocuta,Anda C.; Narayanan,Vijay; Steegen,An L.; Surendra,Maheswaren, CMOS silicide metal gate integration.
  5. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  6. Bin Yu, Fabrication of a wide metal silicide on a narrow polysilicon gate structure.
  7. Yu Bin, Fabrication of a wide metal silicide on a narrow polysilicon gate structure.
  8. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  17. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  18. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  19. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  20. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  21. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  22. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  23. Lou, Chine-Gie, Method for forming salicide process.
  24. Tao, Hun-Jan; Chiu, Yuan-Hung, Method for gate formation with improved spacer profile control.
  25. Visokay, Mark R.; Yu, Shaofeng, Method of enhancing drive current in a transistor.
  26. Deshpande, Sadanand V.; Doris, Bruce B.; Jammy, Rajarao; Ma, William H., Method of fabricating SiO2 spacers and annealing caps.
  27. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  28. Ku Ja-Hum,KRX ; Lee Soo-Geun,KRX ; Kim Chul-Sung,KRX ; Seo Tae-Wook,KRX ; Lee Eung-Joon,KRX ; Chung Joo-Hyuk,KRX, Method of forming self-aligned silicide in semiconductor device.
  29. Jun, Jin-won; Cheong, Kong-soo; Shin, Jeong-ho, Method of forming thick metal silicide layer on gate electrode.
  30. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  31. Mehrad,Freidoon; Yu,Shaofeng; Tran,Joe G., Method to obtain fully silicided poly gate.
  32. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  33. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  34. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  35. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  36. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  37. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  38. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  39. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  40. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  41. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  42. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  43. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  44. Kammler,Thorsten; Wieczorek,Karsten; Schaller,Matthias, Polysilicon line having a metal silicide region enabling linewidth scaling including forming a second metal silicide region on the substrate.
  45. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  46. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  47. Chang, Peter L. D.; Doyle, Brian S., Self-aligned contacts for transistors.
  48. Thomas S. Rupp ; Jeffrey P. Gambino ; Peter Hoh ; Senthil Srinivasan FR, Semiconductor contact and method of forming the same.
  49. Wang, Yu-Piao, Semiconductor device having a lower parasitic capacitance.
  50. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  51. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  52. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  53. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  54. Nandakumar, Mahalingam; Chatterjee, Amitava; Riley, Terrence J., Sidewall spacer pullback scheme.
  55. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  56. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  57. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  58. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  59. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  60. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  61. Dokumaci, Omer H.; Doris, Bruce B.; Purtell, Robert J., Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation.
  62. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  63. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트