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Processor and information processing apparatus with a reconfigurable circuit

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-093/18   
미국특허분류(USC) 712/226 ; 712/209 ; 712/229
출원번호 US-0038834 (1998-03-12)
우선권정보 JP0059566 (1997-03-13)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
인용정보 피인용 횟수 : 59  인용 특허 : 6
초록
▼

Part or all of an instruction decoder is constructed of a first reconfigurable circuit wherein a circuit structure thereof can be changed according to an external signal. Further, a second reconfigurable circuit which is connected to output side of a register file as part of processing unit and wherein a circuit structure thereof can be changed according to an external signal is preliminarily provided. For special use, to achieve a predetermined operating function, the second reconfigurable circuit is reconstructed by the external signal. Further, a part...

대표
청구항
▼

[ What is claimed is:] [1.] An information processing apparatus comprising:a processor including an instruction decoder for decoding an instruction to be executed and at least one function unit for executing the instruction using source data according to a result of decoding of the instruction decoder;a reconfigurable circuit provided outside the processor and reconfigured to a dedicated operating circuit for executing a particular operating function;a memory assigned with a part of addresses in an address space of a main memory; anda control circuit pro...

이 특허에 인용된 특허 (6)

  1. Dockser Kenneth A. Data processor system with instruction substitution filter for deimplementing instructions. USP1999015862370.
  2. Potash Hanan (La Jolla CA) Levin Burton L. (San Diego CA) Chan Stephen J. C. (San Diego CA). Digital computer having programmable structure. USP1982084346438.
  3. Groves Stanley E. (Round Rock TX). Instruction set modifier register. USP1980114236204.
  4. Bartkowiak John G. ; Tran Thang M.. Microprocessor configured to detect memory operations having data addresses indicative of a boundary between instructio. USP1999075930489.
  5. Azekawa Yoshifumi (Hyogo JPX). Microprogram control circuit. USP1994095345570.
  6. Borkenhagen John Michael ; Flynn William Thomas ; Hillier ; III Philip Rodgers ; Wottreng Andrew Henry. System for modifying microprocessor operations independently of the execution unit upon detection of preselected opcodes. USP1998085790843.

이 특허를 인용한 특허 피인용횟수: 59

  1. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  10. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  11. Peting,Mark. Apparatus and method for correcting signal imbalances using complex multiplication. USP2006067069284.
  12. Lais,Eric; Greenberg,Mark; Shah,Manish. Apparatus and method for decode arbitration in a multi-stream multimedia system. USP2006047035355.
  13. Greenberg,Mark; Shah,Manish. Apparatus and method for efficient decoder normalization. USP2006107131054.
  14. Greenberg,Mark; Shah,Manish. Apparatus and method for saturating decoder values. USP2006077073118.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  19. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2013048412915.
  20. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  21. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  22. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  23. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  24. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  25. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  26. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  27. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  28. Peting,Mark. Frequency drift compensation across multiple broadband signals in a digital receiver system. USP2008067382838.
  29. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  30. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  31. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  32. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  33. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  34. Wang,Albert; Rowen,Christopher; Rosenthal,Bernard. High-performance hybrid processor with configurable execution units. USP2007047200735.
  35. Okamoto,Minoru; Ueda,Katsuhiko. Information processing apparatus and information processing method. USP2006067058792.
  36. Okamoto,Minoru; Ueda,Katsuhiko. Inserting decoder reconfiguration instruction for routine with limited number of instruction types recoded for reduced bit changes. USP2007107287149.
  37. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  38. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  39. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  40. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  41. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  42. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  43. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  44. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  45. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  46. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  47. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  48. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  49. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  50. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  51. Dujardin, Eric; Gay-Bellile, Olivier. Multimodule device with static behavior. USP2005096940921.
  52. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  53. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  54. Peting,Mark. System and method for concurrently demodulating and decoding multiple data streams. USP2007077251294.
  55. Shah,Manish; Greenberg,Mark. System and method for shared decoding. USP2007017161994.
  56. Greenberg,Mark; Shah,Manish. System and method for shared decoding using a data replay scheme. USP2007017167531.
  57. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  58. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  59. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.

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