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Robust post Cu-CMP IMD process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0349849 (1999-07-08)
발명자 / 주소
  • Liu Chung-Shi,TWX
  • Yu Chen-Hua,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 38  인용 특허 : 11

초록

A method is provided for cleaning exposed copper surfaces in damascene structures after chemical mechanical polishing of the copper. In a first embodiment exposed copper is annealed in a forming gas environment, a mixture of hydrogen and nitrogen, after chemical mechanical polishing, or other etchin

대표청구항

[ What is claimed is:] [1.] A method of passivating a copper damascene structure, comprising:providing a wafer having a layer of first dielectric formed thereon;etching trenches in said layer of first dielectric;depositing a layer of barrier metal on said layer of first dielectric and on all sides a

이 특허에 인용된 특허 (11)

  1. Teong Su-Ping (Singapore SGX), Etch stop for copper damascene process.
  2. Cronin John Edward, Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same.
  3. Filipiak Stanley M. (Pflugerville TX) Gelatos Avgerinos (Austin TX), Method for capping copper in semiconductor devices.
  4. Nogami Takeshi ; Chan Simon, Method for reducing electromigration in a copper interconnect.
  5. Venkatraman Ramnath (Austin TX), Method of alloying an interconnect structure with copper.
  6. Venkatraman Ramnath ; Weitzman Elizabeth J. ; Fiordalice Robert W., Method of forming an interconnect structure.
  7. Chan Lap ; Zheng Jia Zhen,SGX, Method of manufacturing copper interconnect with top barrier layer.
  8. Hoshino Kazuhiro (Tokyo JPX), Method of producing semiconductor device.
  9. Gelatos Avgerinos V. (Austin TX) Fiordalice Robert W. (Austin TX), Process for forming copper interconnect structure.
  10. Kadomura Shingo (Kanagawa JPX), Process for forming copper wiring.
  11. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (38)

  1. Chikarmane,Vinay B.; Tsang,Chi Hwa, Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing.
  2. Klawuhn, Erich R.; Rozbicki, Robert; Dixit, Girish A., Apparatus and methods for deposition and/or etch selectivity.
  3. Klawuhn,Erich R.; Rozbicki,Robert; Dixit,Girish A., Apparatus and methods for deposition and/or etch selectivity.
  4. Pradhan, Anshu A.; Rozbicki, Robert, Atomic layer profiling of diffusion barrier and metal seed layers.
  5. Pradhan, Anshu A.; Rozbicki, Robert, Atomic layer profiling of diffusion barrier and metal seed layers.
  6. Shaviv, Roey; Gopinath, Sanjay; Holverson, Peter; Pradhan, Anshu A., Conformal films on semiconductor substrates.
  7. Shaviv, Roey; Gopinath, Sanjay; Holverson, Peter; Pradhan, Anshu A., Conformal films on semiconductor substrates.
  8. Wu, Hui-Jung; Juliano, Daniel R.; Wu, Wen; Dixit, Girish, Deposition of doped copper seed layers having improved reliability.
  9. Dulkin, Alexander; Vijayendran, Anil; Yu, Tom; Juliano, Daniel R., Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer.
  10. Noguchi, Junji; Ohashi, Naohumi; Saito, Tatsuyuki, Fabrication method for semiconductor integrated circuit device.
  11. Noguchi, Junji; Asaka, Shoji; Konishi, Nobuhiro; Ohashi, Naohumi; Maruyama, Hiroyuki, Fabrication method of semiconductor integrated circuit device.
  12. Noguchi,Junji; Asaka,Shoji; Konishi,Nobuhiro; Ohashi,Naohumi; Maruyama,Hiroyuki, Fabrication method of semiconductor integrated circuit device.
  13. Hoshino, Tomohisa; Vezin, Vincent; Chung, Gishi, Fabrication process of a semiconductor device including a CVD process of a metal film.
  14. Yin,Zhiping; Zielinski,Eden; Fishburn,Fred, Low temperature nitride used as Cu barrier layer.
  15. Yin,Zhiping; Zielinski,Eden; Fishburn,Fred, Low temperature nitride used as Cu barrier layer.
  16. Pradhan, Anshu A.; Hayden, Douglas B.; Kinder, Ronald L.; Dulkin, Alexander, Method and apparatus for increasing local plasma density in magnetically confined plasma.
  17. Danek, Michal; Rozbicki, Robert, Method for depositing a diffusion barrier for copper interconnect applications.
  18. Rozbicki, Robert T.; Danek, Michal; Klawuhn, Erich R., Method of depositing a diffusion barrier for copper interconnect applications.
  19. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing a diffusion barrier for copper interconnect applications.
  20. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing a diffusion barrier for copper interconnect applications.
  21. Dulkin, Alexander; Rairkar, Asit; Greer, Frank; Pradhan, Anshu A.; Rozbicki, Robert, Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer.
  22. Rozbicki, Robert, Methods and apparatus for resputtering process that improves barrier coverage.
  23. Rozbicki, Robert; van Schravendijk, Bart; Mountsier, Thomas; Wu, Wen, Multistep method of depositing metal seed layers.
  24. Rozbicki, Robert; van Schravendijk, Bart; Mountsier, Tom; Wu, Wen, Multistep method of depositing metal seed layers.
  25. Rozbicki, Robert T.; Powell, Ronald Allan; Klawuhn, Erich; Danek, Michal; Levy, Karl B.; Reid, Jonathan David; Khosla, Mukul; Broadbent, Eliot K., Passivation of copper in dual damascene metalization.
  26. Caubet, Pierre; Gregoire, Magali, Process for forming integrated circuit comprising copper lines.
  27. Kailasam, Sridhar; Rozbicki, Robert; Yu, Chentao; Hayden, Douglas, Resputtering process for eliminating dielectric damage.
  28. Juliano, Daniel R., Selective resputtering of metal seed layers.
  29. Noguchi,Junji; Ohashi,Naohumi; Saito,Tatsuyuki, Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device.
  30. Noguchi, Junji; Ohashi, Naofumi; Takeda, Kenichi; Saito, Tatsuyuki; Yamaguchi, Hizuru; Owada, Nobuo, Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device.
  31. Noguchi, Junji; Ohashi, Naofumi; Takeda, Kenichi; Saito, Tatsuyuki; Yamaguchi, Hizuru; Owada, Nobuo, Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device.
  32. Noguchi, Junji; Ohashi, Naofumi; Takeda, Kenichi; Saito, Tatsuyuki; Yamaguchii, Hizuru; Owada, Nobuo, Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device.
  33. Noguchi, Junji; Ohashi, Naofumi; Takeda, Kenichi; Saito, Tatsuyuki; Yamaguchii, Hizuru; Owada, Nobuo, Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device.
  34. Noguchi, Junji; Ohashi, Naofumi; Takeda, Kenichi; Saito, Tatsuyuki; Yamaguchii, Hizuru; Owada, Nobuo, Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device.
  35. Noguchi, Junji; Ohashi, Naofumi; Takeda, Kenichi; Saito, Tatsuyuki; Yamaguchii, Hizuru; Owada, Nobuo, Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device.
  36. Noguchi, Junji; Ohashi, Naofumi; Takeda, Kenichi; Saito, Tatsuyuki; Yamaguchii, Hizuru; Owada, Nobuo, Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device.
  37. Bailey, III,Andrew D.; Lohokare,Shrikant P., System and method for surface reduction, passivation, corrosion prevention and activation of copper surface.
  38. Kinder, Ronald L.; Pradhan, Anshu A., Use of ultra-high magnetic fields in resputter and plasma etching.
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