초록 ▼

A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A metal interconnection is disposed parallel to an upper layer of the element region. A source line SL is arr

A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A metal interconnection is disposed parallel to an upper layer of the element region. A source line SL is arranged at intervals of plural bit lines BL. The source line is led to a source line contact through a conductive member composed of a low-resistance metal in the same manner as a bit line contact.

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor device comprising:a semiconductor substrate of a first conductivity type;a first element separating region including a first trench formed on said semiconductor substrate and a first insulation layer buried in said first trench;a second element separating

[ What is claimed is:] [1.] A semiconductor device comprising:a semiconductor substrate of a first conductivity type;a first element separating region including a first trench formed on said semiconductor substrate and a first insulation layer buried in said first trench;a second element separating region including a second trench formed on said semiconductor substrate and a second insulating layer buried in said second trench;an element region arranged between said first and second element separating regions;a memory cell string arranged in said element region and having at least one memory cell;first and second contact plugs;a first source line configured to supply a predetermined voltage to said memory cell string via said first contact plug and being arranged in a direction crossing said element region, and said first and second element separating regions;a bit line configured to transfer data from/to said memory cell string via said second contact plug, said bit line being arranged above said first source line in a direction parallel to said element region; anda second source line electrically connected to said first source line and arranged in a layer in which said bit line is formed in parallel with said second source line in a direction crossing said first source line.