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Semiconductor apparatus having wiring groove and contact hole in self-alignment manner 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/535
출원번호 US-0224173 (1998-12-31)
우선권정보 JP0212332 (1996-08-12)
발명자 / 주소
  • Inohara Masahiro,JPX
  • Shibata Hideki,JPX
  • Matsuno Tadashi,JPX
출원인 / 주소
  • Kabushiki Kaisha Toshiba, JPX
대리인 / 주소
    Hogan & Hartson, LLP
인용정보 피인용 횟수 : 32  인용 특허 : 19

초록

A semiconductor apparatus and a process for fabricating the same according to the invention permit reduction in width of a wiring pattern of the semiconductor apparatus and in distance between wiring elements. A stopper film and an insulating film are provided on a substrate. The etching rate of RIE

대표청구항

[ What is claimed is:] [1.] A semiconductor apparatus comprising:a first conductive region provided at one of a region in a semiconductor substrate and a region on the semiconductor substrate;a second conductive region provided above the first conductive region;an interlayer insulating film provided

이 특허에 인용된 특허 (19)

  1. Yoo Chue-San (Taipei) Lin Ting-Hwang (Hsin-Chu) Kuo Sui-Hei (Hsin-Chu TWX), Contact sidewall tapering with argon sputtering.
  2. Motonami Kaoru (Hyogo JPX) Suizu Katumi (Hyogo JPX), Contact structure for interconnection in semiconductor devices and manufacturing method thereof.
  3. Chung Henry Wei-Ming (Cupertino CA), Fabrication of integrated circuits with borderless vias.
  4. Roberts Ceredig ; Srinivasan Anand ; Sandhu Gurtej ; Sharan Sujit, Facet etch for improved step coverage of integrated circuit contacts.
  5. Lee Kuo-hua (Lower Macungie Township ; Lehigh County PA) Polanco Samuel E. (Lower Macungie Township ; Lehigh County PA), Integrated circuits having stepped dielectric regions.
  6. Kim Jae-woo (Suwon KRX) Kim Joon (Seoul KRX) Kim Jin-hong (Suwon KRX), Interconnecting method for semiconductor device.
  7. Yeh Jenn L. (Saratoga CA), Internal bridging contact.
  8. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  9. Jain Ajay ; Lucas Kevin, Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC).
  10. Fiordalice Robert W. (Austin TX) Maniar Papu D. (Austin TX) Klein Jeffrey L. (Austin TX), Method for forming inlaid interconnects in a semiconductor device.
  11. Takahumi Tokunaga (Tokorozawa JPX) Masatoshi Tsuneoka (Ohme JPX) Hiroyuki Akimori (Ohme JPX) Mitsuaki Horiuch (Hachiohji JPX), Method for forming metal layer interconnects using stepped via walls.
  12. Chung Seong Woo,KRX, Method for forming sloped contact hole for semiconductor device.
  13. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  14. Zhang Hongyong,JPX, Method of fabricating semiconductor device.
  15. Matsuura Masazumi,JPX, Method of making a semiconductor device.
  16. Matsuura Masazumi (Hyogo-ken JPX), Semiconductor device and method of fabricating the same.
  17. Cochran William T. (New Tripoli PA) Garcia Agustin M. (Allentown PA) Hills Graham W. (Allentown PA) Yeh Jenn L. (Macungie PA), Semiconductor devices having multi-level metal interconnects.
  18. Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA), Simplified dual damascene process for multi-level metallization and interconnection structure.
  19. Chung U-in (Suwon KRX) Kim Jae-duk (Kyungki-do KRX) Hong Chang-ki (Suwon KRX), Wire forming method for semiconductor device.

이 특허를 인용한 특허 (32)

  1. Lytle,Steven A., Dual damascene process with no passing metal features.
  2. Sell, Bernhard; Golonzka, Oleg, Method of forming stacked trench contacts and structures formed thereby.
  3. Sell, Bernhard; Golonzka, Oleg, Method of forming stacked trench contacts and structures formed thereby.
  4. Sell, Bernhard; Golonzka, Oleg, Method of forming stacked trench contacts and structures formed thereby.
  5. Sell, Bernhard; Golonzka, Oleg, Method of forming stacked trench contacts and structures formed thereby.
  6. Watanabe, Kenichi, Method of manufacturing a semiconductor device having groove-shaped via-hole.
  7. Tran,Luan C.; Fishburn,Fred D., Methods of forming CMOS constructions.
  8. Tran,Luan C.; Fishburn,Fred D., Methods of forming electrical connections for semiconductor constructions.
  9. Ohtake, Hiroto; Hayashi, Yoshihiro, Multilayer wiring structure, semiconductor device, pattern transfer mask and method for manufacturing multilayer wiring structure.
  10. Horita, Katsuyuki; Kuroi, Takashi; Itoh, Yasuyoshi; Shiozawa, Katsuomi, Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer.
  11. Aoyama,Junichi, Semiconductor device and method of manufacturing the same.
  12. Watanabe,Kenichi, Semiconductor device for preventing defective filling of interconnection and cracking of insulating film.
  13. Watanabe, Kenichi, Semiconductor device having groove-shaped pattern.
  14. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  15. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  16. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  17. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  18. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  19. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  20. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  21. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  22. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  23. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  24. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  25. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  26. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  27. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  28. Watanabe, Kenichi, Semiconductor device having groove-shaped via-hole.
  29. Watanabe, Kenichi, Semiconductor device including two groove-shaped patterns.
  30. Watanabe, Kenichi, Semiconductor device including two groove-shaped patterns.
  31. Watanabe, Kenichi, Semiconductor device including two groove-shaped patterns that include two bent portions.
  32. Umemoto, Takeshi, Semiconductor device with multi-layer interlayer dielectric film.
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