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Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/4763
출원번호 US-0387954 (1999-09-01)
우선권정보 KR0059418 (1998-12-28)
발명자 / 주소
  • Lee Soo-cheol,KRX
  • Ahn Jong-hyon,KRX
  • Lee Hyae-ryoung,KRX
출원인 / 주소
  • Samsung Electronics Co., Ltd., KRX
대리인 / 주소
    Myers Bigel Sibley & Sajovec
인용정보 피인용 횟수 : 24  인용 특허 : 10

초록

Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart conductive layers and an array of spaced apart insulating islands in the third continuous conductive layer that extend therethro

대표청구항

[ What is claimed is:] [1.] An internal structure of a bonding pad for an integrated circuit having an array of bonding pads thereon, the internal structure of a bonding pad comprising:first and second spaced apart conductive layers;a third continuous conductive layer between the first and second sp

이 특허에 인용된 특허 (10)

  1. Hsiao Ming-Shan,TWX, Bonding pad structure and method thereof.
  2. Heim Dorothy A. (San Jose CA), Composite bond pads for semiconductor devices.
  3. Shiue Ruey-Yun (Hsin-Chu TWX) Wu Wen-Teng (Hsin-Chu TWX) Shieh Pi-Chen (Hsinchu TWX) Liu Chin-Kai (Hsin-Chu TWX), Method of forming bond pad structure for the via plug process.
  4. Eichelberger Charles W. (Schenectady NY), Multichip integrated circuit modules.
  5. Hsuan Min-Chih,TWX ; Liou Fu-Tai,TWX, Package-free bonding pad structure.
  6. Bryant Frank R. (Denton TX) Chen Fusen E. (Milpitas CA), Semiconductor bond pad structure and method.
  7. Fujiki Noriaki,JPX ; Yamashita Takashi,JPX, Semiconductor device and bonding pad structure therefor.
  8. Satoh Shinichi (Hyogo JPX) Ozaki Hiroji (Hyogo JPX) Kimura Hiroshi (Hyogo JPX) Wakamiya Wataru (Hyogo JPX) Tanaka Yoshinori (Hyogo JPX), Semiconductor device having bonding pad comprising buffer layer.
  9. Nozaki Masahiko (Hyogo JPX), Semiconductor device structure including multiple interconnection layers with interlayer insulating films.
  10. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (24)

  1. Chin Chiu Hsia TW; Bing-Yue Tsui TW; Tsung-Ju Yang TW; Tsung Yao Chu TW, Bonding pad and method for manufacturing it.
  2. Hsia, Chin Chiu; Tsui, Bing-Yue; Yang, Tsung-Ju; Chu, Tsung Yao, Bonding pad and method for manufacturing it.
  3. Cho,Tai Heui; Kang,Hyuck Jin; Kim,Min Chul; Kim,Byung Yoon, Bonding pad structure of a semiconductor device.
  4. Cho, Tai-Heui; Kang, Hyuck-Jin; Kim, Min-Chul; Kim, Byung-Yoon, Bonding pad structure of a semiconductor device and method for manufacturing the same.
  5. Venkitachalam, Girish; Rahim, Irfan; McElheny, Peter John, Integrated circuit bond pad structures.
  6. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  7. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  8. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  9. Kuo,Yian Liang; Lin,Yu Chang, Integrated circuit package bond pad having plurality of conductive members.
  10. Ming-Dou Ker TW; Hsin-Chin Jiang TW, Low-capacitance bonding pad for semiconductor device.
  11. Dias,Rajen; Chandran,Biju, Microelectronic device interconnects.
  12. Hunter, Stevan G.; Rasmussen, Bryce A.; Ruud, Troy L., Pad over interconnect pad structure design.
  13. Takada, Shuichi; Kawakami, Shinya, Semiconductor device.
  14. Kim, Jung Sam, Semiconductor device and method for forming the same.
  15. Watanabe, Kenichi; Ikeda, Masanobu; Kimura, Takahiro, Semiconductor device and method for manufacturing the same.
  16. Ishii, Junya, Semiconductor device and test method for manufacturing same.
  17. Ishii, Junya, Semiconductor device and test method for manufacturing same.
  18. Watanabe, Kenichi, Semiconductor device capable of suppressing current concentration in pad and its manufacture method.
  19. Watanabe,Kenichi, Semiconductor device capable of suppressing current concentration in pad and its manufacture method.
  20. Hashimoto, Shin; Mimura, Tadaaki, Semiconductor device with multilayered metal pattern.
  21. Hashimoto,Shin; Mimura,Tadaaki, Semiconductor device with multilayered metal pattern.
  22. Kwon, Dong Whee; Lee, Jin Hyuk; Song, Yun Heub; Kang, Sa Yoon, Semiconductor devices with bonding pads having intermetal dielectric layer of hybrid configuration and methods of fabricating the same.
  23. Yiu,Ho Yin; Fan,Fu Jier; Wu,Yu Jui; Wang,Aaron; Wang,Hsiang Wei; Lin,Huang Sheng; Chen,Ming Hsien; Shiue,Ruey Yun, Top via pattern for bond pad structure.
  24. Park, Jae Soo; Subramanyam, Chivukula; Chua, Thow Phock; Lee, Hong Lim, Via-sea layout integrated circuits.
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