초록 ▼

Power consumption in medical and battery powered devices is reduced through the use and operation of pipeline architecture in a digital signal processor, microcontroller or microprocessor by operating such devices at clock frequencies tailored to conserve power while preserving computational and exe

Power consumption in medical and battery powered devices is reduced through the use and operation of pipeline architecture in a digital signal processor, microcontroller or microprocessor by operating such devices at clock frequencies tailored to conserve power while preserving computational and executional performance. The digital signal processor, microcontroller or microprocessor can be operated at lower clock frequencies relative to those that would be required by one of such processors to complete the multiple functions within a predetermined time period but having no pipeline architecture. With reduced clock frequency, power consumption is reduced. Further, with reduced clock speed, supply voltages applied to such processors may also be reduced.

대표청구항 ▼

[ I claim:] [1.] A medical device comprising:at least one circuit operable to execute a plurality of instructions, the at least one circuit comprising a processing device, the processing device being operable to execute the plurality of instructions, each of the plurality of instructions being execu

[ I claim:] [1.] A medical device comprising:at least one circuit operable to execute a plurality of instructions, the at least one circuit comprising a processing device, the processing device being operable to execute the plurality of instructions, each of the plurality of instructions being executed during an associated predetermined time period prior to a subsequent time period in which another of the plurality of instructions is executed, the processing device being operable to operate simultaneously upon each of two or more instructions such that substantially the entire associated predetermined time period is used to execute at least one instruction prior to the subsequent time period in which another of the plurality of instructions is executed, the at least one circuit being operable for executing at least one of the plurality of instructions during a predetermined number of clock cycles, each of the plurality of instructions comprising at least first and second portions, the at least one circuit comprising pipeline circuitry capable of substantially simultaneously receiving and outputting in parallel at least one of each of the corresponding respective portions of two or more of the plurality of instructions;a clock source for providing clock signals at a plurality of clock frequencies, the clock source being operatively connected to control the at least one circuit at a clock frequency such that substantially the entire predetermined time period is used to execute the at least one instruction, the at least one instruction being executed just prior to the subsequent time period;wherein the clock frequency is such that the power consumed within the predetermined time period by the at least one circuit in performance of executing each of the plurality of instructions is less than the power that would be consumed if the at least one circuit comprised no pipeline circuitry and were to receive, execute and output each of the plurality of instructions serially.