초록 ▼

An electronic packaging module for bonding of power semiconductor devices is produced. The semiconductor device is mounted on a base, and enclosed by a frame and lid. The lid is an insulating substrate having a conductive pattern with protuberances on the conductive pattern of the substrate. The pro

An electronic packaging module for bonding of power semiconductor devices is produced. The semiconductor device is mounted on a base, and enclosed by a frame and lid. The lid is an insulating substrate having a conductive pattern with protuberances on the conductive pattern of the substrate. The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the metallization pads of semiconductor devices. The metal protuberances are bonded to the semiconductor device joining it to the lid, and through the conductive pattern of the lid connecting the device to the input/output contacts of the package.

대표청구항 ▼

[ I claim:] [1.] A package for a semiconductor chip having at least one semiconductor device, wherein a first surface of the chip is bonded to a base, the base being attached to a frame, and the frame attached to a lid to enclose the chip, the chip having at least one contact pad on its second surfa

[ I claim:] [1.] A package for a semiconductor chip having at least one semiconductor device, wherein a first surface of the chip is bonded to a base, the base being attached to a frame, and the frame attached to a lid to enclose the chip, the chip having at least one contact pad on its second surface, characterized in that:the lid comprises a rigid, planar, insulating substrate having a conductive pattern at least on a first surface facing the chip, the conductive pattern of the lid being electrically connected to the chip through soft, ductile, metal protuberances between the chip and the lid, the number of protuberances connected to a contact pad being sufficient to minimize the contact resistance and the power lost as heat (I.sup.2 R) between the chip and the lid, and minimize the current density on the surface of the chip.