초록 ▼

The invention provides adaptive threshold circuits for comparators, whereby the threshold voltage adapts to characteristics of the input signal. In one embodiment, the steady-state threshold voltage stored on a peak-detector capacitor is generated by ratioing the base-emitter voltages of two emitter

The invention provides adaptive threshold circuits for comparators, whereby the threshold voltage adapts to characteristics of the input signal. In one embodiment, the steady-state threshold voltage stored on a peak-detector capacitor is generated by ratioing the base-emitter voltages of two emitter-follower transistors. As the input signal varies, the threshold voltage follows the input signal. Voltage-controlled current sources sense the amplitude of the input signal, and adjust the amplitude of the threshold voltage by controlling the voltage dropped across a resistor. A feedback signal that indicates the state of the comparator output is coupled to the adaptive threshold circuit to provide hysteresis. In another embodiment, the threshold voltage is determined by the voltage drop across a first resistor. Voltage-controlled current sources sense the amplitude of the input signal, and adjust the amplitude of the threshold voltage by controlling the voltage dropped across a second resistor.

대표청구항 ▼

[ I claim:] [1.] An adaptive threshold circuit that generates first and second output signals, at least one of which varies responsive to an input signal applied to the adaptive threshold circuit comprising:an input signal node to which the input signal is applied;first and second signal paths coupl

[ I claim:] [1.] An adaptive threshold circuit that generates first and second output signals, at least one of which varies responsive to an input signal applied to the adaptive threshold circuit comprising:an input signal node to which the input signal is applied;first and second signal paths coupled to the input signal node, the first signal path having a first output node at which the first output signal is generated responsive to the input signal, and the second signal path having a second output node at which the second output signal is generated responsive to the input signal, wherein proportioned values of circuit elements in the first and second signal paths establish a first predetermined relationship between the first and second output signals;a third signal path coupled to a first bias signal node and to at least one of the first and second signal paths, the third signal path conducting a first compensating signal responsive to the input signal comparing in a predetermined manner to a bias signal at the first bias signal node, the first compensating signal establishing a second predetermined relationship between the first and second output signals;a fourth signal path coupled to at least one of the first and second signal paths, the fourth signal path conducting a second compensating signal responsive to (a) the first and second output signals comparing in a predetermined manner to one another, and (b) at least one of the first and second output signals comparing in a predetermined manner to a bias signal, the second compensating signal establishing a third predetermined relationship between the first and second output signals.