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Process to manufacture continuous metal interconnects 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/441
출원번호 US-0163847 (1998-09-30)
발명자 / 주소
  • Hussein Makarem A.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 45  인용 특허 : 24

초록 ▼

A method of forming an interconnection that includes introducing a barrier material in a via of a dielectric to a circuit device on a substrate in such a manner to deposit the barrier material on the circuit device, introducing a seed material into the via in manner that leaves the barrier material

대표청구항 ▼

[ What is claimed is:] [1.] A method of forming an interconnection, comprising:introducing a barrier material in a via of a dielectric to a circuit device on a substrate in such a manner to deposit the barrier material on the circuit device;introducing a seed material into the via in a manner that l

이 특허에 인용된 특허 (24)

  1. Lesh ; deceased Nathan George (LATE OF Bethlehem PA) BY Merchants National Bank of Allentown ; executor (Allentown PA) Morabito Joseph Michael (Bethlehem PA) Thomas ; III John Henry (Pickerington OH), Conduction system for thin film and hybrid integrated circuits.
    상세보기
  2. Dixit Pankaj (Sunnyvale CA) Sliwa Jack (Los Altos Hills CA) Klein Richard K. (Mountain View CA) Sander Craig S. (Mountain View CA) Farnaam Mohammad (Santa Clara CA), Contact plug and interconnect employing a barrier lining and a backfilled conductor material.
    상세보기
  3. Klein Richard K. ; Erb Darrell ; Avanzino Steven ; Cheung Robin ; Luning Scott ; Tracy Bryan ; Gupta Subhash ; Lin Ming-Ren, Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device.
    상세보기
  4. Bai Gang ; Fraser David B., Diffusion barrier for electrical interconnects in an integrated circuit.
    상세보기
  5. Ting Chiu H. (Saratoga CA) Paunovic Milan (Port Washington NY), Electroless deposition for IC fabrication.
    상세보기
  6. August Melvin C. (Chippewa Falls WI) Shepherd Lloyd T. (Eau Claire WI) Kruchowski James N. (Eau Claire WI), High power, high density interconnect method and apparatus for integrated circuits.
    상세보기
  7. Crank Sue E. (Coppell TX), Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer.
    상세보기
  8. Chakravorty Kishore K. (Issaquah WA) Tanielian Minas H. (Bellevue WA), Interconnect structures having tantalum/tantalum oxide layers.
    상세보기
  9. Mikagi Kaoru (Tokyo JPX), Method for fabricating semiconductor device with interconnections buried in trenches.
    상세보기
  10. Liou Fu-Tai (Carrollton TX) Miller Robert O. (The Colony TX) Farohani Mohammed M. (Carrollton TX) Han Yu-Pin (Dallas TX), Method for forming a contact/VIA.
    상세보기
  11. Ho Yu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Emesh Ismail T. (Cumberland CAX), Method for forming interconnect structures for integrated circuits.
    상세보기
  12. Gelatos Avgerinos V. (Austin TX), Method for forming metallization in an integrated circuit.
    상세보기
  13. Chan Lap ; Zheng Jia Zhen,SGX, Method of manufacturing copper interconnect with top barrier layer.
    상세보기
  14. Chang Kenneth (Hopewell Junction NY) Czornyj George (Poughkeepsie NY) Kumar Ananda H. (Hopewell Junction NY) Steimel Heinz O. (Fishkill NY), Multi layer thin film wiring process featuring self-alignment of vias.
    상세보기
  15. Parrillo Louis C. (Austin TX) Klein Jeffrey L. (Austin TX), Process for fabricating a semiconductor device having an improved metal interconnect structure.
    상세보기
  16. Cooper Kent J. (Austin TX) Woo Michael P. (Austin TX) Ray Wayne J. (Austin TX), Process for forming a contact structure.
    상세보기
  17. Huang Hung-Chang W. (San Jose CA) Totta Paul A. (Poughkeepsie NY), Process for improved contact stud structure for semiconductor devices.
    상세보기
  18. Gilton Terry L. (Boise ID) Tuttle Mark E. (Boise ID) Cathey David A (Boise ID), Process for metallizing integrated circuits with electrolytically-deposited copper.
    상세보기
  19. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
    상세보기
  20. De Bruin Leendert (Eindhoven NLX) Verhaar Robertus D. J. (Eindhoven NLX) Van Laarhoven Josephus M. F. G. (Eindhoven NLX), Selectively plating conductive pillars in manufacturing a semiconductor device.
    상세보기
  21. Miyata Masahiro (Urayasu JPX) Ezawa Hirokazu (Tokyo JPX) Ogure Naoaki (Tokyo JPX) Tsujimura Manabu (Yokohama JPX) Ohdaira Takeyuki (Fujisawa JPX) Inoue Hiroaki (Machida JPX) Ikeda Yukio (Tokyo JPX), Semiconductor device and method for manufacturing the same.
    상세보기
  22. Gardner Mark I. ; Hause Fred N., Semiconductor fabrication employing copper plug formation within a contact area.
    상세보기
  23. Young Peter L. (South Barrington IL) Cech Jay (Elmhurst IL) Li Kin (Lombard IL), Thin-film electrical connections for integrated circuits.
    상세보기
  24. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
    상세보기

이 특허를 인용한 특허 (45)

  1. Chikarmane,Vinay B.; Tsang,Chi Hwa, Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing.
    상세보기
  2. Cunningham,James A., Copper interconnect systems.
    상세보기
  3. Cunningham,James A., Copper interconnect systems which use conductive, metal-based cap layers.
    상세보기
  4. Cunningham,James A., Copper interconnect systems which use conductive, metal-based cap layers.
    상세보기
  5. Cunningham,James A., Copper interconnect systems which use conductive, metal-based cap layers.
    상세보기
  6. Tetsuo Matsuda JP; Hisashi Kaneko JP, Film formation method.
    상세보기
  7. Farrar, Paul A., Integrated circuit and seed layers.
    상세보기
  8. Farrar,Paul A., Integrated circuit and seed layers.
    상세보기
  9. Farrar,Paul A., Integrated circuit and seed layers.
    상세보기
  10. Lee, Ming Han; Chen, Hai-Ching; Lee, Hsiang-Huan; Bao, Tien-I; Teng, Chi-Lin, Interconnect structure including a continuous conductive body.
    상세보기
  11. Dubin, Valery M.; Thomas, Christopher D.; McGregor, Paul; Datta, Madhav, Interconnect structures and a method of electroless introduction of interconnect structures.
    상세보기
  12. Dubin, Valery M.; Cheng, Chin-Chang; Hussein, Makarem; Nguyen, Phi L.; Brain, Ruth A., Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs.
    상세보기
  13. Ueno, Kazuyoshi, Manufacturing method of a semiconductor device.
    상세보기
  14. Choi, Hyung Bok; Park, Jong Bum; Lee, Kee Jeung; Lee, Jong Min, Method for fabricating capacitor of semiconductor device.
    상세보기
  15. Cyril Cabral, Jr. ; Chao-Kun Hu ; Sandra Guy Malhotra ; Fenton Read McFeely ; Stephen Mark Rossnagel ; Andrew Herbert Simon, Method for forming an open-bottom liner for a conductor in an electronic structure and device formed.
    상세보기
  16. Marathe, Amit P.; Wang, Pin-Chin Connie; Woo, Christy Mei-Chu, Method for forming conductor reservoir volume for integrated circuit interconnects.
    상세보기
  17. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
    상세보기
  18. Shih, Tsu; Hung, Kun Ku; Tung, Wen-Hun; Chiou, Wen-Chin, Method for preventing or reducing anodic Cu corrosion during CMP.
    상세보기
  19. Dubin, Valery M.; Thomas, Christopher D.; McGregor, Paul; Datta, Madhav, Method of electroless introduction of interconnect structures.
    상세보기
  20. Preusse, Axel; Friedemann, Michael; Seidel, Robert; Freudenberg, Berit, Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime.
    상세보기
  21. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  22. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  23. Sinha, Nishant, Methods for forming conductive vias in semiconductor device components.
    상세보기
  24. Sinha, Nishant, Methods for forming conductive vias in semiconductor device components.
    상세보기
  25. Sinha, Nishant, Methods for forming conductive vias in semiconductor device components.
    상세보기
  26. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  27. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  28. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  29. Farnworth, Warren M.; McDonald, Steven M.; Sinha, Nishant; Hiatt, William M., Methods of fabricating substrates including at least one conductive via.
    상세보기
  30. Farnworth,Warren M.; McDonald,Steven M.; Sinha,Nishant; Hiatt,William M., Methods of fabricating substrates including at least one conductive via.
    상세보기
  31. Farnworth, Warren M.; McDonald, Steven M.; Sinha, Nishant; Hiatt, William M., Methods of fabricating substrates including one or more conductive vias.
    상세보기
  32. Cunningham, James A., Methods of manufacturing copper interconnect systems.
    상세보기
  33. Kirby,Kyle K.; Farnworth,Warren M., Methods of plating via interconnects.
    상세보기
  34. Ahn,Kie Y.; Forbes,Leonard; Eldridge,Jerome M., Multilevel copper interconnect with double passivation.
    상세보기
  35. Choi,Hok Kin; Thirumala,Vani; Dubin,Valery; Cheng,Chin chang; Zhong,Ting, Preparation of electroless deposition solutions.
    상세보기
  36. Sinha,Nishant, Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias.
    상세보기
  37. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
    상세보기
  38. Machkaoutsan, Vladimir; Song, Stanley Seungchul; Zhu, John Jianhong; Bao, Junjing; Xu, Jeffrey Junhao; Badaroglu, Mustafa; Nowak, Matthew Michael; Yeap, Choh Fei, Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices.
    상세보기
  39. Sinha, Nishant, Semiconductor device components with conductive vias and systems including the components.
    상세보기
  40. Kirby, Kyle K.; Farnworth, Warren M., Semiconductor devices and in-process semiconductor devices having conductor filled vias.
    상세보기
  41. Farrar, Paul A., Structures and methods to enhance copper metallization.
    상세보기
  42. Farrar, Paul A., Structures and methods to enhance copper metallization.
    상세보기
  43. Farrar,Paul A., Structures and methods to enhance copper metallization.
    상세보기
  44. Farrar,Paul A., Structures and methods to enhance copper metallization.
    상세보기
  45. Dubin,Valery M.; Cheng,Chin Chang; Hussein,Makarem; Nguyen,Phi L.; Brain,Ruth A., Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures.
    상세보기

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