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Field emission display 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • A01J-063/00
출원번호 US-0286267 (1999-04-05)
발명자 / 주소
  • Cathey David A.
  • Watkins Charles
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Wells, St. John, Roberts, Gregory & Matkin P.S.
인용정보 피인용 횟수 : 33  인용 특허 : 31

초록

A flat-panel field emission display comprises a luminescent faceplate, a rigid backplate, and an interposed or sandwiched emitter or cathode plate. A positioning spacer or connector ridge is formed on the rear surface of the faceplate to space the cathode plate a fixed distance behind the faceplate.

대표청구항

[ What is claimed is:] [1.] A flat-panel field emission display, comprising:a faceplate having a rear surface;a cathode plate spaced from the faceplate rear surface and having a plurality of emitters facing the faceplate rear surface, the cathode plate having an outermost periphery;a backplate havin

이 특허에 인용된 특허 (31)

  1. Wallace Robert M. (Richardson TX) Gnade Bruce E. (Dallas TX) Kirk Wiley P. (Richardson TX), Anode plate for flat panel display having silicon getter.
  2. Peterson James R. (Garland TX) Majors Edward M. (Plano TX), Apparatus and method of forming aluminum balls for ball bonding.
  3. Yamamoto Jiro (Tokyo JPX), Connector for interconnecting a grid to a grid drive in a chip-in fluorescent display panel.
  4. Banno Yoshikazu (Ebina JPX) Nakata Kohei (Machida JPX) Nomura Ichiro (Atsugi JPX) Kaneko Tetsuya (Yokohama JPX) Nakamura Naoto (Isehara JPX), Display apparatus having first and second internal spaces.
  5. Brodie Ivor (Palo Alto CA) Gernick Henry R. (Pleasanton CA) Holland Christopher E. (Redwood City CA) Moessner Helmut A. (Saratoga CA), Field emission cathode based flat panel display having polyimide spacers.
  6. Kane Robert C. (Woodstock IL) Jaskie James E. (Scottsdale AZ) Parker Norman W. (Wheaton IL), Field emission device display with vacuum seal.
  7. Cathey David A. ; Watkins Charles, Field emission display.
  8. Kane Robert C. (Woodstock IL), Field emission display device employing an integral planar field emission control device.
  9. Yamazaki Fumio (Hirakata JPX) Moriyama Yuichi (Ibaragi JPX) Nakatani Toshifumi (Moriguchi JPX) Imai Kanji (Takatsuka JPX), Flat panel display device and a method of making the same.
  10. Morrison Paul-David (Round Rock TX), Hermetic semiconductor device having jumper leads.
  11. Nakayama Akira (Tokyo JPX) Inoue Junichi (Ibaragi JPX) Yamamoto Masanobu (Kanagawa JPX), Image display device with cathode panel and gas absorbing getters.
  12. Taylor Robert H. (Richardson TX), Interconnect for use in flat panel display.
  13. Cathey David A. ; Watkins Charles, Internal plate flat-panel field emission display.
  14. Fahlen Theodore S. (San Jose CA) Duboc ; Jr. Robert M. (Menlo Park CA) Lovoi Paul A. (Saratoga CA), Internal support structure for flat panel device.
  15. Mohacsi Ferenc (Kalamazoo MI), Low pressure gas discharge lamps with low profile sealing cover plate.
  16. Holmberg Scott H. (Pleasanton CA), Matrix addressing arrangement for a flat panel display with field emission cathodes.
  17. Spindt Charles A. (Menlo Park CA) Holland Christopher E. (Redwood City CA), Matrix-addressed flat panel display.
  18. Spindt Charles A. (Menlo Park CA) Holland Christopher E. (Redwood City CA), Matrix-addressed flat panel display.
  19. Brodie Ivor (Palo Alto CA) Gurnick Henry R. (Pleasanton CA) Holland Christopher E. (Redwood City CA) Moessner Helmut A. (Saratoga CA), Method for providing polyimide spacers in a field emission panel display.
  20. Thomas Michael E. (Milpitas CA), Method of bonding semiconductor chips to a substrate.
  21. Wallace Robert M. (Dallas TX) Gnade Bruce E. (Dallas TX) Shen Chi-Cheong (Richardson TX) Levine Jules D. (Dallas TX) Taylor Robert H. (Richardson TX), Method of making a field emission device anode plate having an integrated getter.
  22. Cathey David A. (Boise ID) Watkins Charles (Meridian ID) Gochnour Derek (Boise ID), Method of mechanical and electrical substrate connection.
  23. Sandhu Gurtej S. (Boise ID), Method to form self-aligned tips for flat panel displays.
  24. Cathey David A. (Boise ID) Watkins Charles (Meridian ID) Gochnour Derek (Boise ID), Methods of mechanical and electrical substrate connection.
  25. Stansbury Darryl M., Multi-layer electrical interconnection methods and field emission display fabrication methods.
  26. Stansbury Darryl M., Multi-layer electrical interconnection structures.
  27. Stansbury Darryl M. (Boise ID), Multi-layer electrical interconnection structures and fabrication methods.
  28. Nagano Shinichirou (Hyogo JPX) Yamanaka Takashi (Hyogo JPX) Uchiyama Osamu (Hyogo JPX), Plasma display panel and a process for producing the same.
  29. Butt Sheldon H. (Godfrey IL) Cherukuri Satyam C. (West Haven CT), Process for producing a hermetically sealed package for an electrical component containing a low amount of oxygen and wa.
  30. Borel Michel (Le Touvet FRX) Boronat Jean-Francois (Grenoble FRX) Meyer Robert (St Ismier FRX) Rambaud Philippe (Grenoble FRX), Process for the production of a display means by cathodoluminescence excited by field emission.
  31. Lovoi Paul A. (Saratoga CA), Self supporting flat video display.

이 특허를 인용한 특허 (33)

  1. Farrar,Paul A.; Geusic,Joseph, Buried conductor patterns formed by surface transformation of empty spaces in solid state materials.
  2. Russ,Benjamin Edward; Barger,Jack, Carbon cathode of a field emission display with in-laid isolation barrier and support.
  3. Russ,Benjamin Edward; Barger,Jack, Carbon cathode of a field emission display with integrated isolation barrier and support on substrate.
  4. Seon,Hyeong Rae; Lee,Jae Hoon, Electron emission display having a spacer.
  5. Fukutomi,Naoki; Tsubomatsu,Yoshiaki; Inoue,Fumio; Yamazaki,Toshio; Ohhata,Hirohito; Hagiwara,Shinsuke; Taguchi,Noriyuki; Nomura,Hiroshi, Fabrication process of semiconductor package and semiconductor package.
  6. Russ, Benjamin Edward; Barger, Jack, Field emission display using gate wires.
  7. Russ, Benjamin Edward; Barger, Jack, Field emission display utilizing a cathode frame-type gate.
  8. Russ,Benjamin E.; Barger,Jack, Field emission display utilizing a cathode frame-type gate and anode with alignment method.
  9. Forbes, Leonard, Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers.
  10. Forbes, Leonard, Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers.
  11. Forbes, Leonard; Geusic, Joseph E., Gettering using voids formed by surface transformation.
  12. Forbes, Leonard; Geusic, Joseph E., Gettering using voids formed by surface transformation.
  13. Forbes, Leonard; Geusic, Joseph E., Gettering using voids formed by surface transformation.
  14. Forbes,Leonard; Geusic,Joseph E., Gettering using voids formed by surface transformation.
  15. Russ,Benjamin Edward; Barger,Jack; Kawasaki,Kenichi, Image display device incorporating driver circuits on active substrate and other methods to reduce interconnects.
  16. Forbes,Leonard, Localized strained semiconductor on insulator.
  17. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials.
  18. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials.
  19. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon.
  20. Stansbury, Darryl, Multiple level printing in a single pass.
  21. Shiraishi, Akinori; Koizumi, Naoyuki; Murayama, Kei; Sakaguchi, Hideaki; Sunohara, Masahiro; Taguchi, Yuichi; Higashi, Mitsutoshi, Sealed structure and method of fabricating sealed structure and semiconductor device and method of fabricating semiconductor device.
  22. Forbes, Leonard, Semiconductor on insulator structure.
  23. Forbes,Leonard, Semiconductors bonded on glass substrates.
  24. Forbes,Leonard, Silicon oxycarbide substrates for bonded silicon on insulator.
  25. Russ,Benjamin Edward; Barger,Jack, Spacer-less field emission display.
  26. Forbes,Leonard, Strained Si/SiGe/SOI islands and processes of making same.
  27. Forbes,Leonard, Strained Si/SiGe/SOI islands and processes of making same.
  28. Forbes, Leonard; Geusic, Joseph E., Three-dimensional photonic crystal waveguide structure and method.
  29. Forbes,Leonard; Geusic,Joseph E., Three-dimensional photonic crystal waveguide structure and method.
  30. Forbes,Leonard, Ultra-thin semiconductors bonded on glass substrates.
  31. Forbes,Leonard, Ultra-thin semiconductors bonded on glass substrates.
  32. Kim, Dae Yong; Kim, Hyun Tak, Vacuum channel transistor and manufacturing method thereof.
  33. Forbes,Leonard, Wafer gettering using relaxed silicon germanium epitaxial proximity layers.
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