초록 ▼

A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more

A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifics which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed. The VLIW memory (VIM) can be further partitioned into separate memories each associated with a function decode-and-execute unit. With a second execute VLIW instruction XV2, each functional unit's VIM can be independently addressed thereby removing duplicate SIWs within the functional unit's VIM. This provides a further optimization of the VLIW storage thereby allowing the use of smaller VLIW memories in cost sensitive applications.

대표청구항 ▼

[ We claim:] [1.] An indirect very long instruction word (VLIW) processor comprisinga plurality of execution units capable of performing a plurality of distinct operations in parallel;a VLIW memory (VIM) for storing VLIWs;an execute VLIW (XNV instruction containing an offset value; andan addressing

[ We claim:] [1.] An indirect very long instruction word (VLIW) processor comprisinga plurality of execution units capable of performing a plurality of distinct operations in parallel;a VLIW memory (VIM) for storing VLIWs;an execute VLIW (XNV instruction containing an offset value; andan addressing mechanism for providing access to each memory entry in VIM, said memory entries each containing at least one instruction slot associated with a unique execution unit, said addressing mechanism comprising a base address register and adder employed in connection with each processing element operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access.