초록 ▼

The present invention relates to multilevel integrated circuit interconnection techniques. An integrated circuit having a number of electronic components along a semiconductor substrate and a first connection layer having a first number of conductors in selective electrical contact with the componen

The present invention relates to multilevel integrated circuit interconnection techniques. An integrated circuit having a number of electronic components along a semiconductor substrate and a first connection layer having a first number of conductors in selective electrical contact with the components is provided. A first insulative layer is formed on the first connection layer with a first pattern of openings therethrough. A second connection layer is established that has a second number of conductors selectively interconnected to the first conductors through the first pattern of openings. A second insulative layer is formed on the first connection layer with a second pattern of openings therethrough. A third connection layer is formed on the second insulative layer having a third dielectric and a third number of conductors selectively interconnecting the second conductors. The first and second insulative layers are preferably etch selective to a dielectric included in the first, second, and third connection layers; and crossover, crossunder, or local interconnects are formed in a different connection layer than routing interconnects to facilitate higher interconnection density.

대표청구항 ▼

[ What is claimed is:] [1.] A method of integrated circuit manufacture, comprising:providing a number of electronic components along a semiconductor substrate, and a first connection layer comprised of a first dielectric and a first number of conductors in selective electrical contact with the compo

[ What is claimed is:] [1.] A method of integrated circuit manufacture, comprising:providing a number of electronic components along a semiconductor substrate, and a first connection layer comprised of a first dielectric and a first number of conductors in selective electrical contact with the components;forming a first insulative layer on the first connection layer with a first pattern of openings therethrough;establishing a second connection layer comprised of a second dielectric and a second number of conductors selectively interconnecting the first conductors through the first pattern of openings;forming a second insulative layer on the second connection layer with a second pattern of openings therethrough; andestablishing a third connection layer on the second insulative layer comprised of a third dielectric and a third number of conductors selectively interconnecting the second conductors, the third dielectric being etch selective to the second insulative layer, the second and third conductors being in contact with the second insulative layer, and at least one of the second conductors crossing at least one of the third conductors and being electrically isolated therefrom by the second insulative layer.