초록 ▼

A copper-palladium alloy damascene technology applied to the ultra large scale integration (ULSI) circuits fabrication is disclosed. First, a TaN barrier is deposited over an oxide layer or in terms of the inter metal dielectric (IMD) layer. Then a copper-palladium seed is deposited over the TaN bar

A copper-palladium alloy damascene technology applied to the ultra large scale integration (ULSI) circuits fabrication is disclosed. First, a TaN barrier is deposited over an oxide layer or in terms of the inter metal dielectric (IMD) layer. Then a copper-palladium seed is deposited over the TaN barrier. Furthermore, a copper-palladium gap-fill electroplating layer is electroplated over the dielectric oxide layer. Second, a copper-palladium annealing process is carried out. Then the copper-palladium electroplating surface is planarized by means of a chemical mechanical polishing (CMP) process. Third, the CoWP cap is self-aligned to the planarized copper-palladium alloy surface. Finally, a second IMD layer is deposited over the first IMD layer. Furthermore, a contact hole in the second dielectric layer over said CoWP cap layer is formed, and then the CoWP cap of the first IMD layer is connected with the copper-palladium alloy bottom surface of the second IMD layer directly. The other deposition processes are subsequently performed the same way.

대표청구항 ▼

[ What is claimed is:] [9.] A method of forming a copper-palladium alloy damascene for ultra large scale integration circuits, said method comprising:conformably forming a TaN barrier layer on bottom and sidewall surface of a dielectric layer gap;forming a copper seed layer over the TaN barrier laye

[ What is claimed is:] [9.] A method of forming a copper-palladium alloy damascene for ultra large scale integration circuits, said method comprising:conformably forming a TaN barrier layer on bottom and sidewall surface of a dielectric layer gap;forming a copper seed layer over the TaN barrier layer;forming a copper gap-fill electroplating layer over the dielectric layer;conformably sputtering a palladium layer over said copper electroplating layer followed by a nitrogen gas annealing step to form a copper-palladium alloy;planarizing said copper-palladium alloy by a chemical mechanical polishing step;capping a CoWP cap layer over the planarized copper-palladium alloy surface;forming a second dielectric layer over the dielectric layer; andforming a contact hole in said second dielectric layer over said cap layer.