초록 ▼

Methods and apparatus for implementing single instruction multiple data (SIMD) signal processing operations are described. The apparatus of the present invention include new registers and register arrays which allow data to be accessed at a word as well as sub-word or sub-register level. The registe

Methods and apparatus for implementing single instruction multiple data (SIMD) signal processing operations are described. The apparatus of the present invention include new registers and register arrays which allow data to be accessed at a word as well as sub-word or sub-register level. The registers and register arrays of the present invention may be used when implementing a system based on a SIMD architecture. Registers implemented in accordance with the present invention include a plurality of pass gates that allow an entire n-bit word stored in the register to be accessed and output as a single word or for a sub-word portion of a stored word to be accessed and output. During standard operation the registers are accessed on a word basis. However, during column access operations, e.g., when performing a transpose operation, access is performed on a sub-word basis. The ability to access the registers of the present invention on a word or sub-word level make implementing transpose and various other row/column data manipulation operations possible in a relatively straightforward manner without data buffering. In addition to the novel registers and register arrays of the present invention, various aspects of the present invention are directed to new and novel SIMD instructions, e.g., SIMD move, add, and move instructions, which support the specification of data to be processed as operands which identify rows or columns of register arrays as opposed to merely identifying registers as done with conventional commands. A transpose command is also supported.

대표청구항 ▼

[ What is claimed is:] [1.] An apparatus, comprising:a first register assembly including:i. a first register having n storage locations, where n is an integer;ii. a first pass gate responsive to a first control signal coupled to a first set of said n storage locations; andiii. a second pass gate res

[ What is claimed is:] [1.] An apparatus, comprising:a first register assembly including:i. a first register having n storage locations, where n is an integer;ii. a first pass gate responsive to a first control signal coupled to a first set of said n storage locations; andiii. a second pass gate responsive to a second control signal coupled to a second set of said n storage locations, at least one of the storage locations included in the second set being different from the storage locations included in the first set, the first register assembly outputting the data included in the first set of the n storage locations in response to activation of the first control signal and outputting the data included in the second set of the n storage locations in response to activation of the second control signal.