초록 ▼

A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmissi

A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.

대표청구항 ▼

[ What is claimed is:] [3.] A semiconductor circuit comprising:at least one data storage memory having a control input terminal and a data input terminal;a data processor including a send/receive control bus circuit connected via a control bus line to the memory control input terminal of the at leas

[ What is claimed is:] [3.] A semiconductor circuit comprising:at least one data storage memory having a control input terminal and a data input terminal;a data processor including a send/receive control bus circuit connected via a control bus line to the memory control input terminal of the at least one memory for sending and receiving control signals to and from the at least one memory, and a data line connected to the at least one memory data input terminal for transmitting data signals to and from the at least one memory;a transmission line stub connected to the at least one control bus line at the memory control input terminal for providing a time delay to synchronize the control signals with the data signal;wherein the send/receive control bus circuit includes a drive circuit responsive to a clock signal input to produce control signal pulses, and a detector circuit connected to the driver circuit and to the control bus line, the detector circuit being enabled by the driver circuit to receive pulses from the memory on the control bus line that are time delayed by the transmission line stub and are synchronized with the data signals on the data line.