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Synchronization system for reducing slipping 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04L-025/36
출원번호 US-0997981 (1997-12-24)
우선권정보 CA2217840 (1997-10-09)
발명자 / 주소
  • Zhang Genzao,CAX
  • Smith Roland,CAX
  • Oprea Dan,CAX
  • Ferland Roger,CAX
출원인 / 주소
  • Nortel Networks Limited, CAX
대리인 / 주소
    Measures
인용정보 피인용 횟수 : 27  인용 특허 : 18

초록

An improved local synchronization module which uses Frequency-phase adaptive double locked loop (FPADLL) to control a stable controllable oscillator is disclosed. A single physical feedback loop is implemented which can operate in either a phase locked loop mode or a frequency locked loop mode. The

대표청구항

[ What is claimed is:] [1.] A synchronization system comprising:a reference signal recovery unit for recovering a reference signal, said reference signal having phase and frequency signal characteristics, said recovery unit including a slip buffer;a controllable signal source for producing an output

이 특허에 인용된 특허 (18)

  1. Cloutier Leo, Apparatus and method for correcting jitter in data packets.
  2. Tateishi Kiyoshi,JPX, Cycle slip detector and phase locked loop circuit and digital signal reproducing apparatus using the same.
  3. Crowley Albert T. (Gloucester Township ; Camden County NJ), Digital frequency and phase lock loop.
  4. Kim Yong-Hoe,KRX ; Kang Sug-Geun,KRX, Digital processing phase lock loop for synchronous digital micro-wave apparatus.
  5. Minami Yoichiro (Tokyo JPX), FSK receiver having a PLL local oscillator operable in intermittent operation in accordance with its phase locked state.
  6. Underhill, Michael J.; Walters, Nigel J., Frequency synthesizer of the phase lock loop type.
  7. Whiteside Frank A., Jitter attenuator.
  8. Inagaki Yoshio (Tokyo JPX) Takami Masayuki (Yamato JPX) Kataoka Masahiro (Tokyo JPX) Shibagaki Taro (Tokyo JPX), Master-slave multiplex communication system and PLL circuit applied to the system.
  9. Waters Michael R., Method and apparatus for attenuating jitter in a digital transmission line.
  10. Girardeau ; Jr. James W. (Austin TX), Method and apparatus for controlling a digital phase lock loop and within a cordless telephone.
  11. Grover Wayne D. (Ottawa CAX), Method and apparatus for detecting frame synchronization.
  12. Park Jung-Hee (Kyongki-do KRX), Method and circuit for controlling digital processing phase-locked loop for network synchronization.
  13. Javitt Joel I. (Hillside NJ), Network-controlled reference frequency generator.
  14. Chiao Jennifer Yuan ; Yach Randy L., Phase locked loop with improved lock time and stability.
  15. Onvural Raif O. ; Marin Gerald Arnold, Recovering a clock signal in a multimedia network using time stamps.
  16. Muntz Gary S. ; Jacobs Steven E., SRTS clock recovery system implementing adaptive clock recovery techniques.
  17. Pinto Victor,ILX ; Feldman Neil David,ILX ; Hadas Tzach,ILX ; Zandman Yaakov Arie,ILX, Self-tuning clock recovery phase-locked loop circuit.
  18. Taniguchi Kenshi,JPX ; Takeuchi Tomotaka,JPX ; Tanaka Masatoshi,JPX, Video and audio signal multiplex sending apparatus, receiving apparatus and transmitting apparatus.

이 특허를 인용한 특허 (27)

  1. Wu, Lei; Hu, Timothy, Apparatus and method for providing pre-emphasis to a signal.
  2. Wu,Lei; Sutioso,Henri, Apparatus for clock data recovery.
  3. Wu, Lei; Sutioso, Henri, Circuits, architectures, a system and methods for improved clock data recovery.
  4. Kuwajima, Naoki, Clock generation circuit.
  5. Sutioso, Henri; Wu, Lei, Clock offset compensator.
  6. Sutioso,Henri; Wu,Lei, Clock offset compensator.
  7. Wu, Lei; Hu, Timothy, Device with pre-emphasis based transmission.
  8. Carballo,Juan Antonio; Nowka,Kevin John; Vo,Ivan; Yoo,Seung moon, Digital transmission circuit and method providing selectable power consumption via multiple weighted drive slices.
  9. Carballo, Juan Antonio; Nowka, Kevin John; Vo, Ivan; Yoo, Seung moon, Digital transmission circuit and method providing selectable power consumption via single-ended or differential operation.
  10. Cutler, Robert T., Distributing frequency references.
  11. Carballo, Juan-Antonio; Burns, Jeffrey L., Interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage.
  12. Shapira, Yaniv; Billic, Hrvoje, Method and apparatus for controlling data transfer in a serial-ATA system.
  13. Carballo,Juan Antonio; Burns,Jeffrey L.; Vo,Ivan, Method and apparatus for measuring communications link quality.
  14. Carballo,Juan Antonio; Burns,Jeffrey L.; Vo,Ivan, Method and apparatus for measuring communications link quality.
  15. Chang, Po-Chien, Method and apparatus for providing an interface between a host device and a plurality of storage devices.
  16. Shetty, Naresh B., Methods and systems for transmitting signals differentially and single-endedly across a pair of wires.
  17. Wu, Lei; Hu, Timothy, Programmable pre-emphasis circuit for serial ATA.
  18. Wu, Lei; Hu, Timothy, Programmable pre-emphasis circuit for serial ATA.
  19. Wu,Lei; Hu,Timothy, Programmable pre-emphasis circuit for serial ATA.
  20. Yamazaki, Kiyohiko, Radio signal receiving circuit detecting a synchronizing pattern.
  21. Chang, Po-Chien, Serial/parallel ATA controller and converter.
  22. Chang,Po Chien, Serial/parallel ATA controller and converter.
  23. Laroia, Rajiv; Li, Junyi; Rangan, Sundeep; Uppala, Sathyadev Venkata, Signal construction, detection and estimation for uplink timing synchronization and access control in a multi-access wireless communication system.
  24. Duewer, Bruce; Kamath, Gautham Devendra, Signal-characteristic determined digital-to-analog converter (DAC) filter stage configuration.
  25. Narasimhan, Ravi, Systems and methods for compensating a channel estimate for phase and sampling phase jitter.
  26. Sutioso, Henri; Wu, Lei, Systems and methods for compensating a phase of a local clock of a storage device.
  27. Peng, Kathy L., Techniques to control signal phase.
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