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Flip chip solder bump pad

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B32B-015/20
  • H01L-023/488
출원번호 US-0216769 (1998-12-21)
발명자 / 주소
  • Erickson Curt A
출원인 / 주소
  • Delco Electronics Corporation
대리인 / 주소
    Funke
인용정보 피인용 횟수 : 38  인용 특허 : 10

초록

A method for forming a solder bump pad (22), and more particularly converting a wire bond pad (12) of a surface-mount IC device (10) to a flip chip solder bump pad (22), such that the IC device (10) can be flip-chip mounted to a substrate. The process generally entails an aluminum wire bond pad (12)

대표청구항

[ What is claimed is:] [1.] A flip chip solder bump pad structure on a surface-mount electronic device, the flip chip solder bump pad comprising:an aluminum wire bond pad;a dielectric layer overlying a peripheral surface portion of the aluminum wire bond pad so that an inner surface portion of the a

이 특허에 인용된 특허 (10)

  1. Agarwala Birendra N. (Hopewell Junction NY) Datta Madhav (Yorktown Heights NY) Gegenwarth Richard E. (Poughkeepsie NY) Jahnes Christopher V. (Monsey NY) Miller Patrick M. (Poughkeepsie NY) Nye ; III , Etching processes for avoiding edge stress in semiconductor chip solder bumps.
  2. Wong Kaiser H., Fine flip chip interconnection.
  3. Chiu George W. (Palo Alto CA), Method and apparatus for forming solder balls and solder columns.
  4. Kaussen Franz (Warstein DEX) Figura Martin (Ruethen-Kallenhardt DEX), Method for fixing semiconductor bodies on a substrate using wires.
  5. Satou Tetsuo,JPX ; Ishida Yoshihiro,JPX, Method for forming bump of semiconductor device.
  6. Zakel Elke,DEX ; Aschenbrenner Rolf,DEX ; Ostmann Andreas,DEX ; Kasulke Paul,DEX, Method for galvanic forming of bonding pads.
  7. Dishon Giora J. (Chapel Hill NC), Method of building solder bumps.
  8. Lochon Henri (Saintry-sur-Seine FRX) Robert Georges (La Ferte-Alais FRX), Method of forming metal contact pads and terminals on semiconductor chips.
  9. Agarwala Birendra N. (Hopewell Junction NY), Process of making pad structure for solder ball limiting metallurgy having reduced edge stress.
  10. Ting Chiu H., Sealed semiconductor chip and process for fabricating sealed semiconductor chip.

이 특허를 인용한 특허 (38)

  1. Mohammad Eslamy, Apparatus and method for mounting BGA devices.
  2. Huang, Tai-Chun; Yao, Chih-Hsiang; Hsieh, Ching-Hua, Bond pad for flip chip package.
  3. Lin, Mou-Shiung; Lin, I, Shih-Hsiung, Chip package having a chip combined with a substrate via a copper pillar.
  4. Chen, Ke-Hung; Lin, Shih-Hsiung; Lin, Mou-Shiung, Chip package with dam bar restricting flow of underfill.
  5. Chien, Feng-Lung; Lo, Randy H. Y.; Ke, Chun-chi, Circuit probing contact pad formed on a bond pad in a flip chip package.
  6. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D., Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip.
  7. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D., Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip.
  8. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
  9. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
  10. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
  11. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Cylindrical bonding structure and method of manufacture.
  12. Briere, Michael, Flip chip FET device.
  13. Briere,Michael, Flip chip FET device.
  14. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  15. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  16. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  17. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  18. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  19. Vinciarelli,Patrizio; McCauley,Charles I.; Starenas,Paul V., Low loss, high density array interconnection.
  20. Lin, Mou-Shiung, Metallization structure over passivation layer for IC chip.
  21. Feustel, Frank; Frohberg, Kai; Werner, Thomas, Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom.
  22. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Method for fabricating circuit component.
  23. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
  24. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
  25. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  26. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  27. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  28. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  29. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  30. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  31. Hill, Darrell G.; Bowles, Philip H.; Campbell, Jan; Daly, Terry K.; Fender, Jason R.; Ramanathan, Lakshmi N.; Tracht, Neil T., Microelectronic assembly with back side metallization and method for forming the same.
  32. Brunner, Sebastian; Kaul, Franz; Fischer, Annette, Module substrate and production method.
  33. Huang, Ching-Cheng; Lin, Chuen-Jye; Lei, Ming-Ta; Lin, Mou-Shiung, Reliable metal bumps on top of I/O pads after removal of test probe marks.
  34. Patrick W. Tandy, Selectively coating bond pads.
  35. Zhang, Leilei, Solder ball assembly for a semiconductor device and method of fabricating same.
  36. Zhang,Leilei, Solder ball assembly for a semiconductor device and method of fabricating same.
  37. Lin, Mou-Shiung, Solder interconnect on IC chip.
  38. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
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