초록 ▼

A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integr

A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted a second integrated circuit chip to physically and electrically connect the first integrated circuit chip to the second integrated circuit chip. The first integrated circuit chip has interchip interface circuits connected to the second integrated circuit chip to selectively communicate between internal circuits of the first and second integrated circuit chips or test interface circuits connected to the internal circuits of the first integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. The second integrated circuit chip has input/output interface circuitry to communicate with external circuitry connected to the second integrated circuit chip and to protect said second integrated circuit chip from electrostatic discharge voltages. Further, the second integrated circuit has interchip interface circuits connected to the first integrated circuit chip to communicate between the internal circuits of the first and second integrated circuit chips.

대표청구항 ▼

[ The invention claimed is:] [1.] A method of forming a multiple integrated circuit chip structure comprising the steps of:simultaneously but separately forming internal circuits on a first semiconductor wafer containing plural first integrated circuit chips and a second semiconductor wafer containi

[ The invention claimed is:] [1.] A method of forming a multiple integrated circuit chip structure comprising the steps of:simultaneously but separately forming internal circuits on a first semiconductor wafer containing plural first integrated circuit chips and a second semiconductor wafer containing plural second integrated circuit chips;simultaneously forming test circuits on the first wafer and the second wafer;simultaneously forming interchip interface circuits on the first wafer and the second wafer, whereby forming said interchip interface circuit comprises the steps of:forming an internal interface circuit for transferring electrical signals between a second integrated circuit chip to a first integrated circuit chip;forming a mode select switch having a first terminal connected to an output of the internal interface circuit, a second terminal connected to the internal circuitry of the first integrated circuit chip;forming a mode selector to selectively connect the output of the internal interface circuit to the internal circuitry of the first integrated circuit chip during normal operation and the output of the internal interface circuit to the test circuitry during test and burn-in;forming input/output interface circuits on said second wafer;contacting, stimulating, and examining a response of the test circuits on the first wafer and the test circuits and input/output interface circuits on the second wafer;separating the first wafer into a plurality of separated first integrated circuit chips;contacting with sockets, stimulating and burning-in the plurality of separated first integrated circuit chips for an extended period of time;contacting, stimulating, and examining the plurality of separated first integrated circuit chips;discarding defective first integrated circuit chips;attaching each functioning chip of the first integrated circuit chips to a functioning second integrated circuit chip on the second wafer;separating the second wafer into the plurality of second integrated circuit chips; andcontacting the input/output interface circuits, stimulating, and examining the response of the formed multiple integrated circuit chip structure.