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Method to fabricate high Q inductor by redistribution layer when flip-chip package is employed

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/823
출원번호 US-0556422 (2000-04-24)
발명자 / 주소
  • Tsai Chao-Chieh,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 63  인용 특허 : 7

초록

A new method is provided for the creation of a high Q inductor that can be applied together with the mounting of flip chip semiconductor die on a substrate. The process of the invention starts with a semiconductor surface over which a layer of insulation and intra-metal dielectric have been deposite

대표청구항

[ What is claimed is:] [1.] A method of creating a high-Q inductor on a surface of a semiconductor substrate whereby said substrate is in addition used for mounting of flip chip semiconductor devices, comprising the steps of:providing a semiconductor substrate whereby a surface of said substrate is

이 특허에 인용된 특허 (7)

  1. Bischoff Peter G. ; Stovall Ross W, Interposer with embedded circuitry and method for using the same to package microelectronic units.
  2. Pfeifer Michael J. (Chandler AZ) Marlin George W. (Phoenix AZ), Method of fabricating a flip chip semiconductor device having an inductor.
  3. Tserng Hua Q. (Dallas TX), Method of making flip-chip microwave integrated circuit.
  4. Pedder David John,GB3, Multi-chip module inductor structure.
  5. Smith John W., Semiconductor package with translator for connection to an external substrate.
  6. Yap Daniel (Thousand Oaks CA), Substrate system for optoelectronic/microwave circuits.
  7. Pedder David John,GBX, Trimmable inductor structure.

이 특허를 인용한 특허 (63)

  1. Nickerson,Robert; Ekhlassi,Hamid, Ball grid array copper balancing.
  2. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Chip package.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  4. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
  5. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  6. Irfan M. Rahim, Circuit structure including a passive element formed within a grid array substrate and method for making the same.
  7. Hamamoto, Mitchell M.; Chen, Yi Gao; Tan, Kim Hwee, Device having wire bond and redistribution layer.
  8. Sherazi,Iman; Kovacic,Stephen J., Direct attach optical receiver module and method of testing.
  9. Tang, Yiwu; Jin, Zhang, High Q transformer disposed at least partly in a non-semiconductor substrate.
  10. Woo,Sang hyun; Lee,Kwang du, High frequency inductor having low inductance and low inductance variation and method of manufacturing the same.
  11. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
  12. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
  13. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  14. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  15. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  16. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
  17. Yamamoto,Ryota; Furumiya,Masayuki; Ohkubo,Hiroaki; Nakashiba,Yasutaka, Inductor for semiconductor integrated circuit and method of fabricating the same.
  18. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  19. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  20. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  21. Lin, Yaojian; Marimuthu, Pandi Chelvam, Integrated circuit package system with post-passivation interconnection and integration.
  22. Lin, Yaojin; Marimuthu, Pandi Chelvam, Integrated circuit package system with post-passivation interconnection and integration.
  23. Marimuthu, Pandi Chelvam; Frye, Robert Charles; Lin, Yaojian, Integrated circuit stacking system with integrated passive components.
  24. Ko, Ching-Chung; Lee, Tung-Hsing; Chan, Kuei-Ti; Cheng, Tao; Yang, Ming-Tzong, Integrated inductor.
  25. Crawford, Ankur Mohan; Braunisch, Henning; Nair, Rajendran; Vandentop, Gilroy; Wang, Shan X., Integrated inductor structure and method of fabrication.
  26. Lin, Yaojian; Cao, Haijing; Frye, Robert Charles; Marimuthu, Pandi Chelvam, Integrated passive device system.
  27. Lin, Yaojian; Cao, Haijing; Zhang, Qing; Chen, Kang; Fang, Jianmin, Integrated passive devices.
  28. Chaochieh Tsai TW; Shyhchyi Wong TW, Lossless microstrip line in CMOS process.
  29. Tsai, Chaochieh; Wong, Shyhchyi, Lossless microstrip line in CMOS process.
  30. Ping Liou TW, Method and structure of manufacturing a high-Q inductor with an air trench.
  31. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  32. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  33. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  34. Thomas, Danielle A.; Siegel, Harry Michael; Do Bento Vieira, Antonio A.; Chiu, Anthony M., Method for providing a redistribution metal layer in an integrated circuit.
  35. Thomas,Danielle A.; Siegel,Harry Michael; Vieira,Antonio A. Do Bento; Chiu,Anthony M., Method for providing a redistribution metal layer in an integrated circuit.
  36. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Method of fabricating chip package.
  37. Shunsuke Koyama JP, Mounting structure of semiconductor device, and communication apparatus using the same.
  38. He, Jiangqi; Sankman, Robert L.; Xu, BaoShu; Zeng, Xiang Yin, Packaged spiral inductor structures, processes of making same, and systems containing same.
  39. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  40. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  41. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  42. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
  43. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
  44. Lin, Yaojian, Semiconductor device and method of forming IPD on molded substrate.
  45. Lin, Yaojian, Semiconductor device and method of forming an inductor on polymer matrix composite substrate.
  46. Lin, Yaojian, Semiconductor device and method of forming an inductor on polymer matrix composite substrate.
  47. Minami, Yoshihiro, Semiconductor device with spiral inductor and method for fabricating semiconductor integrated circuit device.
  48. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
  49. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
  50. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
  51. Thomas, Danielle A.; Siegel, Harry Michael; Do Bento Vieira, Antonio A.; Chiu, Anthony M., System for providing a redistribution metal layer in an integrated circuit.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  57. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  58. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  59. Josefosky, John T; Tang, Yiwu; Hayward, Roger, Transformer within wafer test probe.
  60. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
  61. Shen,Lee Cheng, Wafer level packaging structure with inductors and manufacture method thereof.
  62. Hamamoto, Mitchell M.; Chen, Yioao; Tan, Kim Hwee, Wire bond and redistribution layer process.
  63. Hamamoto, Mitchell M.; Gao, Chen Yi; Hwee, Tan Kim, Wire bond and redistribution layer process.
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