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Copper interconnection structure incorporating a metal seed layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/532
출원번호 US-0067851 (1998-04-27)
발명자 / 주소
  • Edelstein Daniel Charles
  • Harper James McKell Edwin
  • Hu Chao-Kun
  • Simon Andrew H.
  • Uzoh Cyprian Emeka
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Trepp
인용정보 피인용 횟수 : 175  인용 특허 : 16

초록 ▼

The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper c

대표청구항 ▼

[ The embodiment of the invention in which an exclusive property or privilege is claimed are defined as follows:] [1.] An interconnection structure for providing electrical connections to an electronic device comprising:a body formed of copper and between about 0.001 and about 10 weight percent of a

이 특허에 인용된 특허 (16)

  1. Farooq Mukta S. (Hopewell Junction NY) Kaja Suryanarayana (Hopewell Junction NY) Perfecto Eric D. (Poughkeepsie NY) White George E. (Hoffman Estates IL), Capped copper electrical interconnects.
    상세보기
  2. Kato Masanori (Tokyo JPX), High-conductivity copper alloys with excellent workability and heat resistance.
    상세보기
  3. Crank Sue E. (Coppell TX), Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer.
    상세보기
  4. Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX, Integrated circuit inductor structure formed employing copper containing conductor winding layer clad with nickel contai.
    상세보기
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    상세보기
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    상세보기
  7. Tao Jiang ; Fang Peng, Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity.
    상세보기
  8. Farooq Mukta S. (Hopewell Junction NY) Kaja Suryanarayana (Hopewell Junction NY) Perfecto Eric D. (Poughkeepsie NY) White George E. (Hoffman Estates IL), Method for forming capped copper electrical interconnects.
    상세보기
  9. Ho Yu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Emesh Ismail T. (Cumberland CAX), Method for forming interconnect structures for integrated circuits.
    상세보기
  10. Nogami Takeshi ; Dubin Valery ; Cheung Robin, Method of electroplating a copper or copper alloy interconnect.
    상세보기
  11. Pan Ju-Don T. (Austin TX), Method of making an electrical multilayer interconnect.
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  12. Kwon Chul-soon,KRX, Methods of fabricating copper interconnects for integrated circuits.
    상세보기
  13. Kawai Michifumi,JPX ; Satoh Ryohei,JPX ; Yamada Osamu,JPX ; Matsuda Eiji,JPX ; Ishino Masakazu,JPX ; Inoue Takashi,JPX ; Sotokawa Hideo,JPX ; Kyoui Masayuki,JPX, Multilayer substrates methods for manufacturing multilayer substrates and electronic devices.
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  14. Ting Chiu ; Dubin Valery, Plated copper interconnect structure.
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  16. Maniar Papu D. (Austin TX) Moazzami Reza (Austin TX) Mogab C. Joseph (Austin TX), Semiconductor device having a reducing/oxidizing conductive material.
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